| Message ID | 20230427162301.1151333-10-patrick@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Implement ISA Manual Table A.6 Mappings | expand |
On 4/27/23 10:22, Patrick O'Neill wrote: > This change brings atomic fences in line with table A.6 of the ISA > manual. > > Relax mem_thread_fence according to the memmodel given. > > 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> > > gcc/ChangeLog: > > * config/riscv/sync.md (mem_thread_fence_1): Change fence > depending on the given memory model. OK jeff
On 4/28/23 11:00, Jeff Law wrote: > > > On 4/27/23 10:22, Patrick O'Neill wrote: >> This change brings atomic fences in line with table A.6 of the ISA >> manual. >> >> Relax mem_thread_fence according to the memmodel given. >> >> 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> >> >> gcc/ChangeLog: >> >> * config/riscv/sync.md (mem_thread_fence_1): Change fence >> depending on the given memory model. > OK > jeff Committed. Patrick
../../gcc/config/riscv/sync.md: In function 'const char* output_479(rtx_def**, rtx_insn*)':
../../gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void function [-Werror=return-type]
66 | [(set (attr "length") (const_int 4))])
| ^
On 5/3/23 14:18, Andreas Schwab via Gcc-patches wrote: > ../../gcc/config/riscv/sync.md: In function 'const char* output_479(rtx_def**, rtx_insn*)': > ../../gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void function [-Werror=return-type] > 66 | [(set (attr "length") (const_int 4))]) > | ^ > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109713
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3e6345e83a3..ba132d8a1ce 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -45,14 +45,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations.
This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)