Show patches with: Submitter = Jeffrey Law       |    State = Action Required       |    Archived = No       |   320 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[committed] Fix RISC-V test after recent vectorizer changes [committed] Fix RISC-V test after recent vectorizer changes - - - - --- 2026-01-15 Jeffrey Law New
[committed] Improve shift loops on the H8 [committed] Improve shift loops on the H8 - - - - --- 2025-12-19 Jeffrey Law New
[committed] Another MAINTAINERS update [committed] Another MAINTAINERS update - - - - --- 2025-12-17 Jeffrey Law New
MAINTAINERS file updates MAINTAINERS file updates - - - - --- 2025-12-11 Jeffrey Law New
[committed] Adjust expected output of new risc-v test [committed] Adjust expected output of new risc-v test - - - - --- 2025-12-06 Jeffrey Law New
[RFA,PR,target/121778] Improving rotation detection [RFA,PR,target/121778] Improving rotation detection - - - - --- 2025-11-30 Jeffrey Law New
[to-be-committed,RISC-V,PR,rtl-optimization/122735] Avoid bogus calls to simplify_subreg [to-be-committed,RISC-V,PR,rtl-optimization/122735] Avoid bogus calls to simplify_subreg - - - - --- 2025-11-26 Jeffrey Law New
[committted,PR,rtl-optimization/122782] Fix out of range shift causing bootstrap failure with ubsan [committted,PR,rtl-optimization/122782] Fix out of range shift causing bootstrap failure with ubsan - - - - --- 2025-11-24 Jeffrey Law New
[committed,PR,122701] Emit fresh reg->reg copy rather than modifying existing insnO [committed,PR,122701] Emit fresh reg->reg copy rather than modifying existing insnO - - - - --- 2025-11-22 Jeffrey Law New
[committed,RISC-V] Fix trivial bootstrap failure on RISC-V [committed,RISC-V] Fix trivial bootstrap failure on RISC-V - - - - --- 2025-11-19 Jeffrey Law New
[committed,PR,rtl-optimization/122575] Fix mode on optimized IOR comparison [committed,PR,rtl-optimization/122575] Fix mode on optimized IOR comparison - - - - --- 2025-11-17 Jeffrey Law New
[to-be-committed,RISC-V] Cleanup zero-extension patterns, generalize zero-extend with shifted opera… [to-be-committed,RISC-V] Cleanup zero-extension patterns, generalize zero-extend with shifted opera… - - - - --- 2025-11-15 Jeffrey Law New
[to-be-committed,RISC-V] Eliminate zero-extension related define_insn_and_splits [to-be-committed,RISC-V] Eliminate zero-extension related define_insn_and_splits - - - - --- 2025-11-15 Jeffrey Law New
[committed] Handle shift-pairs in ext-dce for targets without zero/sign extension insns [committed] Handle shift-pairs in ext-dce for targets without zero/sign extension insns - - - - --- 2025-11-13 Jeffrey Law New
[committed,RISC-V,PR,rtl-optimization/122627] Yet another fix in IRA equivalence array handling [committed,RISC-V,PR,rtl-optimization/122627] Yet another fix in IRA equivalence array handling - - - - --- 2025-11-13 Jeffrey Law New
[to-be-committed,RISC-V] Simplify riscv_extend_to_xmode_reg [to-be-committed,RISC-V] Simplify riscv_extend_to_xmode_reg - - - - --- 2025-11-10 Jeffrey Law New
[to-be-committed,RISC-V,PR,121136] Improve various tests which only need to examine upper bits in a… [to-be-committed,RISC-V,PR,121136] Improve various tests which only need to examine upper bits in a… - - - - --- 2025-11-06 Jeffrey Law New
[to-be-committed,RISC-V,PR,121136] Improve various tests which only need to examine upper bits in a… [to-be-committed,RISC-V,PR,121136] Improve various tests which only need to examine upper bits in a… - - - - --- 2025-11-04 Jeffrey Law New
[to-be-committed,RISC-V,SH,PR,rtl-optimization/67731] Improve logical IOR of single bit bitfields [to-be-committed,RISC-V,SH,PR,rtl-optimization/67731] Improve logical IOR of single bit bitfields - - - - --- 2025-11-01 Jeffrey Law New
[to-be-committed,RISC-V] Reorder ready queue slightly to avoid unnecessary vsetvl instructions [to-be-committed,RISC-V] Reorder ready queue slightly to avoid unnecessary vsetvl instructions - - - - --- 2025-11-01 Jeffrey Law New
[RFA,PR,rtl-optimization/122321,RISC-V] Bounds check another access to ira_reg_equiv array [RFA,PR,rtl-optimization/122321,RISC-V] Bounds check another access to ira_reg_equiv array - - - - --- 2025-10-29 Jeffrey Law New
[to-be-committed,PR,target/116662,RISC-V] Adjust destructive interference size for RISC-V [to-be-committed,PR,target/116662,RISC-V] Adjust destructive interference size for RISC-V - - - - --- 2025-10-29 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/64345,PR,tree-optimization/80770] Improve simple bit extractions … [to-be-committed,RISC-V,PR,target/64345,PR,tree-optimization/80770] Improve simple bit extractions … - - - - --- 2025-10-26 Jeffrey Law New
[committed] Fix minor testsuite scan failures for RISC-V [committed] Fix minor testsuite scan failures for RISC-V - - - - --- 2025-10-20 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/120674] Avoid division by zero in dwarf emitter when vector is no… [to-be-committed,RISC-V,PR,target/120674] Avoid division by zero in dwarf emitter when vector is no… - - - - --- 2025-10-12 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/122147] Avoid creating (subreg (mem)) in RISC-V port [to-be-committed,RISC-V,PR,target/122147] Avoid creating (subreg (mem)) in RISC-V port - - - - --- 2025-10-03 Jeffrey Law New
[to-be-committed,PR,target/122051] Fix pmode_reg_or_uimm5_operand for thead vector [to-be-committed,PR,target/122051] Fix pmode_reg_or_uimm5_operand for thead vector - - - - --- 2025-10-01 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/122106] Add missing predicate on crc expanders [to-be-committed,RISC-V,PR,target/122106] Add missing predicate on crc expanders - - - - --- 2025-10-01 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/121983] Fix unprotected REGNO invocation [to-be-committed,RISC-V,PR,target/121983] Fix unprotected REGNO invocation - - - - --- 2025-09-19 Jeffrey Law New
[RFC,RISC-V] Optimize clear-lowest-set-bit sequence when ctz is nearby [RFC,RISC-V] Optimize clear-lowest-set-bit sequence when ctz is nearby - - - - --- 2025-09-16 Jeffrey Law New
[committed,RISC-V] Adjust ABI specification in recently added Andes tests [committed,RISC-V] Adjust ABI specification in recently added Andes tests - - - - --- 2025-09-12 Jeffrey Law New
[committed] Remove xfail marker on RISC-V test [committed] Remove xfail marker on RISC-V test - - - - --- 2025-08-27 Jeffrey Law New
[committed] RISC-V Testsuite hygiene [committed] RISC-V Testsuite hygiene - - - - --- 2025-08-26 Jeffrey Law New
[committed] Fix RISC-V bootstrap [committed] Fix RISC-V bootstrap - - - - --- 2025-08-26 Jeffrey Law New
[RFA,PR,rtl-optimization/120553] Improve selecting between constants based on sign bit test [RFA,PR,rtl-optimization/120553] Improve selecting between constants based on sign bit test - - - - --- 2025-08-14 Jeffrey Law New
[committed,RISC-V] Don't run tests requiring "B" on designs without "B" [committed,RISC-V] Don't run tests requiring "B" on designs without "B" - - - - --- 2025-08-11 Jeffrey Law New
[to-be-committed,RISC-V] Restrict generic-vector-ooo DFA [to-be-committed,RISC-V] Restrict generic-vector-ooo DFA - - - - --- 2025-07-22 Jeffrey Law New
[to-be-committed,RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md [to-be-committed,RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md - - - - --- 2025-07-21 Jeffrey Law New
[to-be-committed,RISC-V] Avoid propagating constant AVL for theadvector [to-be-committed,RISC-V] Avoid propagating constant AVL for theadvector - - - - --- 2025-07-08 Jeffrey Law New
[committed] Minor fix to gcc.dg/torture/pr120654.c [committed] Minor fix to gcc.dg/torture/pr120654.c - - - - --- 2025-07-08 Jeffrey Law New
[committed,RISC-V] Fix testsuite fallout from check-function-bodies change [committed,RISC-V] Fix testsuite fallout from check-function-bodies change - - - - --- 2025-07-08 Jeffrey Law New
[PR,sanitizer/119356] Cherry pick bugfix from LLVM sanitizer runtime [PR,sanitizer/119356] Cherry pick bugfix from LLVM sanitizer runtime - - - - --- 2025-06-27 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118734] Make using zero-strided loads a uarch tunable [to-be-committed,RISC-V,PR,target/118734] Make using zero-strided loads a uarch tunable - - - - --- 2025-06-24 Jeffrey Law New
[committed,PR,rtl-optimization/120550] Drop REG_EQUAL note after ext-dce transformation [committed,PR,rtl-optimization/120550] Drop REG_EQUAL note after ext-dce transformation - - - - --- 2025-06-22 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/119830] Fix RISC-V codegen on 32bit hosts [to-be-committed,RISC-V,PR,target/119830] Fix RISC-V codegen on 32bit hosts - - - - --- 2025-06-22 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118241] Fix data prefetch predicate/constraint for RISC-V [to-be-committed,RISC-V,PR,target/118241] Fix data prefetch predicate/constraint for RISC-V - - - - --- 2025-06-21 Jeffrey Law New
[to-be-committed,RISC-V] Force several tests to use rocket tuning [to-be-committed,RISC-V] Force several tests to use rocket tuning - - - - --- 2025-06-19 Jeffrey Law New
[to-be-committed,RISC-V] Fix ICE due to splitter emitting constant loads directly [to-be-committed,RISC-V] Fix ICE due to splitter emitting constant loads directly - - - - --- 2025-06-09 Jeffrey Law New
[to-be-committed,RISC-V] Add support for 32bit conditional move source/destinations on rv64 [to-be-committed,RISC-V] Add support for 32bit conditional move source/destinations on rv64 - - - - --- 2025-06-08 Jeffrey Law New
[to-be-committed,RISC-V] Handle 32bit operands in condition for conditional moves [to-be-committed,RISC-V] Handle 32bit operands in condition for conditional moves - - - - --- 2025-06-06 Jeffrey Law New
[committed] Fix compromised ARC test [committed] Fix compromised ARC test - - - - --- 2025-06-06 Jeffrey Law New
[to-be-committed,RISC-V] Improve signed division by 2^n [to-be-committed,RISC-V] Improve signed division by 2^n - - - - --- 2025-06-05 Jeffrey Law New
[to-be-committed,RISC-V] Add andi+bclr synthesis [to-be-committed,RISC-V] Add andi+bclr synthesis - - - - --- 2025-05-24 Jeffrey Law New
[to-be-committed,RISC-V] Clear both upper and lower bits using 3 shifts [to-be-committed,RISC-V] Clear both upper and lower bits using 3 shifts - - - - --- 2025-05-22 Jeffrey Law New
[to-be-committed,RISC-V] Improve (x << C1) + C2 split code [to-be-committed,RISC-V] Improve (x << C1) + C2 split code - - - - --- 2025-05-21 Jeffrey Law New
[committed,RISC-V,PR,target/120333] Remove bogus bext pattern [committed,RISC-V,PR,target/120333] Remove bogus bext pattern - - - - --- 2025-05-19 Jeffrey Law New
[committed,RISC-V] Fix false positive from Wuninitialized [committed,RISC-V] Fix false positive from Wuninitialized - - - - --- 2025-05-19 Jeffrey Law New
[to-be-committed,RISC-V] Avoid multiple assignments to output object [to-be-committed,RISC-V] Avoid multiple assignments to output object - - - - --- 2025-05-18 Jeffrey Law New
[to-be-committed,RISC-V] Fix ICE due to bogus use of gen_rtvec [to-be-committed,RISC-V] Fix ICE due to bogus use of gen_rtvec - - - - --- 2025-05-17 Jeffrey Law New
[to-be-committed,RISC-V] Avoid setting output object more than once in IOR/XOR synthesis [to-be-committed,RISC-V] Avoid setting output object more than once in IOR/XOR synthesis - - - - --- 2025-05-16 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/120223] Don't use bset/binv for XTHEADBS [to-be-committed,RISC-V,PR,target/120223] Don't use bset/binv for XTHEADBS - - - - --- 2025-05-13 Jeffrey Law New
[to-be-committed,V2,RISC-V] Synthesize more efficient IOR/XOR sequences [to-be-committed,V2,RISC-V] Synthesize more efficient IOR/XOR sequences - - - - --- 2025-05-08 Jeffrey Law New
[to-be-committed,RISC-V] Synthesize more efficient IOR/XOR sequences [to-be-committed,RISC-V] Synthesize more efficient IOR/XOR sequences - - - - --- 2025-05-08 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/120137] Don't create out-of-range permutation constants [to-be-committed,RISC-V,PR,target/120137] Don't create out-of-range permutation constants - - - - --- 2025-05-07 Jeffrey Law New
[to-be-committed,RISC-V] Avoid unnecessary andi with -1 argument [to-be-committed,RISC-V] Avoid unnecessary andi with -1 argument - - - - --- 2025-05-06 Jeffrey Law New
[RISC-V,PR,target/119971] Avoid losing shift count masking [RISC-V,PR,target/119971] Avoid losing shift count masking - - - - --- 2025-05-05 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/119971] Avoid losing shift count masking [to-be-committed,RISC-V,PR,target/119971] Avoid losing shift count masking - - - - --- 2025-05-05 Jeffrey Law New
[V2,to-be-committed,RISC-V] Trivial permutation constant derivation [V2,to-be-committed,RISC-V] Trivial permutation constant derivation - - - - --- 2025-05-04 Jeffrey Law New
[to-be-committed,RISC-V] Adjust rvv tests after recent jump threading change [to-be-committed,RISC-V] Adjust rvv tests after recent jump threading change - - - - --- 2025-05-04 Jeffrey Law New
[to-be-committed] Adjust rvv tests after recent jump threading change [to-be-committed] Adjust rvv tests after recent jump threading change - - - - --- 2025-05-04 Jeffrey Law New
[to-be-committed,RISC-V] Adjust testcases and finish register move costing fix [to-be-committed,RISC-V] Adjust testcases and finish register move costing fix - - - - --- 2025-05-03 Jeffrey Law New
[RISC-V] Fix missed bext discovery [RISC-V] Fix missed bext discovery - - - - --- 2025-04-18 Jeffrey Law New
[committed,RISC-V] Fix more fallout from combine.c changes -- correct patch attached this time [committed,RISC-V] Fix more fallout from combine.c changes -- correct patch attached this time - - - - --- 2025-04-09 Jeffrey Law New
[committed,RISC-V] Fix more fallout from combine.c changes [committed,RISC-V] Fix more fallout from combine.c changes - - - - --- 2025-04-09 Jeffrey Law New
[RISC-V] Fix unreported code quality regression with single bit manipulations [RISC-V] Fix unreported code quality regression with single bit manipulations - - - - --- 2025-03-17 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256,V4] Fix minor code quality regression in reassociated arit… [to-be-committed,RISC-V,PR,target/116256,V4] Fix minor code quality regression in reassociated arit… - - - - --- 2025-03-16 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256,V3] Fix minor code quality regression in reassociated arit… [to-be-committed,RISC-V,PR,target/116256,V3] Fix minor code quality regression in reassociated arit… - - - - --- 2025-03-16 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256,V2] Fix minor code quality regression in reassociated arit… [to-be-committed,RISC-V,PR,target/116256,V2] Fix minor code quality regression in reassociated arit… - - - - --- 2025-03-16 Jeffrey Law New
[rtl-optimization/117467] Mark FP destinations as dead [rtl-optimization/117467] Mark FP destinations as dead - - - - --- 2025-03-09 Jeffrey Law New
[rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce [rtl-optimization/117467] Avoid unnecessarily marking things live in ext-dce - - - - --- 2025-03-09 Jeffrey Law New
[to-be-committed,RISC-V,PR,rtl-optimization/119099] Avoid infinite loop in ext-dce. [to-be-committed,RISC-V,PR,rtl-optimization/119099] Avoid infinite loop in ext-dce. - - - - --- 2025-03-06 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256] Fix minor code quality regression in reassociated arithme… [to-be-committed,RISC-V,PR,target/116256] Fix minor code quality regression in reassociated arithme… - - - - --- 2025-03-02 Jeffrey Law New
[RFC,PR,tree-optimization/117829] Bogus Warray-bounds warning [RFC,PR,tree-optimization/117829] Bogus Warray-bounds warning - - - - --- 2025-02-19 Jeffrey Law New
[committed,PR,middle-end/113525] Drop obsolete options from documentation [committed,PR,middle-end/113525] Drop obsolete options from documentation - - - - --- 2025-02-19 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118248] Avoid bogus alloca call in RISC-V backend [to-be-committed,RISC-V,PR,target/118248] Avoid bogus alloca call in RISC-V backend - - - - --- 2025-02-16 Jeffrey Law New
[RFA,PR,tree-optimization/98028] Use relationship between operands to simplify SUB_OVERFLOW [RFA,PR,tree-optimization/98028] Use relationship between operands to simplify SUB_OVERFLOW - - - - --- 2025-02-12 Jeffrey Law New
[RFA,PR,target/115478] Accept ADD, IOR or XOR when combining objects with no bits in common [RFA,PR,target/115478] Accept ADD, IOR or XOR when combining objects with no bits in common - - - - --- 2025-02-10 Jeffrey Law New
[committed,RISC-V,PR,target/115123] Fix testsuite fallout from sinking heuristic change [committed,RISC-V,PR,target/115123] Fix testsuite fallout from sinking heuristic change - - - - --- 2025-02-09 Jeffrey Law New
[committed,PR,middle-end/117263] Avoid unused-but-set warning in genautomata [committed,PR,middle-end/117263] Avoid unused-but-set warning in genautomata - - - - --- 2025-02-09 Jeffrey Law New
[committed,RISC-V] Fix risc-v expected test output after recent iv changes [committed,RISC-V] Fix risc-v expected test output after recent iv changes - - - - --- 2025-02-06 Jeffrey Law New
[committed,PR,tree-optimization/114277] Fix missed optimization for multiplication against boolean … [committed,PR,tree-optimization/114277] Fix missed optimization for multiplication against boolean … - - - - --- 2025-02-01 Jeffrey Law New
[committed,PR,target/114085] Fix H8 constraint issue which led to ICE [committed,PR,target/114085] Fix H8 constraint issue which led to ICE - - - - --- 2025-01-28 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256] Improve handling of single bit constants [to-be-committed,RISC-V,PR,target/116256] Improve handling of single bit constants - - - - --- 2025-01-25 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate [to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate - - - - --- 2025-01-21 Jeffrey Law New
[committed,PR,target/116256] Adjust expected output in a couple testcases [committed,PR,target/116256] Adjust expected output in a couple testcases - - - - --- 2025-01-20 Jeffrey Law New
[to-be-committed,PR,target/114442] Add reservations for all insn types to xiangshan-nanhu model [to-be-committed,PR,target/114442] Add reservations for all insn types to xiangshan-nanhu model - - - - --- 2025-01-20 Jeffrey Law New
[committed,PR,rtl-optimization/107455] Eliminate unnecessary constant load - v3 [committed,PR,rtl-optimization/107455] Eliminate unnecessary constant load - v3 - - - - --- 2025-01-13 Jeffrey Law New
[committed] Fix regression in ft32 port after recent switch table adjustments [committed] Fix regression in ft32 port after recent switch table adjustments - - - - --- 2025-01-07 Jeffrey Law New
[committed,PR,testsuite/118055] Trivial testsuite adjustment for m68k target [committed,PR,testsuite/118055] Trivial testsuite adjustment for m68k target - - - - --- 2025-01-07 Jeffrey Law New
[RFC/RFA,PR,tree-optimization/92539] Improve code and avoid Warray-bounds false positive [RFC/RFA,PR,tree-optimization/92539] Improve code and avoid Warray-bounds false positive - - - - --- 2025-01-03 Jeffrey Law New
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