mbox series

[gcc13,backport,00/12] RISC-V: Implement ISA Manual Table A.6 Mappings

Message ID 20230725180206.284777-1-patrick@rivosinc.com
Headers show
Series RISC-V: Implement ISA Manual Table A.6 Mappings | expand

Message

Patrick O'Neill July 25, 2023, 6:01 p.m. UTC 
Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
Jeff Law.
If there aren't any objections I'll commit this cherry-picked series
on Thursday (July 27th).

Patchset on trunk:
https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/
First commit: f37a36bce81b50a43ec1613c1d08d803642f7506

Also includes bugfix from:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109713
commit: 4bd434fbfc7865961a8e10d7e9601b28765ce7be

[1] https://inbox.sourceware.org/gcc/mhng-b7423fca-67ec-4ce4-9694-4e062632ceb0@palmer-ri-x1c9/T/#t

Martin Liska (1):
  riscv: fix error: control reaches end of non-void function

Patrick O'Neill (11):
  RISC-V: Eliminate SYNC memory models
  RISC-V: Enforce Libatomic LR/SC SEQ_CST
  RISC-V: Enforce subword atomic LR/SC SEQ_CST
  RISC-V: Enforce atomic compare_exchange SEQ_CST
  RISC-V: Add AMO release bits
  RISC-V: Strengthen atomic stores
  RISC-V: Eliminate AMO op fences
  RISC-V: Weaken LR/SC pairs
  RISC-V: Weaken mem_thread_fence
  RISC-V: Weaken atomic loads
  RISC-V: Table A.6 conformance tests

 gcc/config/riscv/riscv-protos.h               |   3 +
 gcc/config/riscv/riscv.cc                     |  66 ++++--
 gcc/config/riscv/sync.md                      | 196 ++++++++++++------
 .../riscv/amo-table-a-6-amo-add-1.c           |  15 ++
 .../riscv/amo-table-a-6-amo-add-2.c           |  15 ++
 .../riscv/amo-table-a-6-amo-add-3.c           |  15 ++
 .../riscv/amo-table-a-6-amo-add-4.c           |  15 ++
 .../riscv/amo-table-a-6-amo-add-5.c           |  15 ++
 .../riscv/amo-table-a-6-compare-exchange-1.c  |   9 +
 .../riscv/amo-table-a-6-compare-exchange-2.c  |   9 +
 .../riscv/amo-table-a-6-compare-exchange-3.c  |   9 +
 .../riscv/amo-table-a-6-compare-exchange-4.c  |   9 +
 .../riscv/amo-table-a-6-compare-exchange-5.c  |   9 +
 .../riscv/amo-table-a-6-compare-exchange-6.c  |  10 +
 .../riscv/amo-table-a-6-compare-exchange-7.c  |   9 +
 .../gcc.target/riscv/amo-table-a-6-fence-1.c  |  14 ++
 .../gcc.target/riscv/amo-table-a-6-fence-2.c  |  15 ++
 .../gcc.target/riscv/amo-table-a-6-fence-3.c  |  15 ++
 .../gcc.target/riscv/amo-table-a-6-fence-4.c  |  15 ++
 .../gcc.target/riscv/amo-table-a-6-fence-5.c  |  15 ++
 .../gcc.target/riscv/amo-table-a-6-load-1.c   |  16 ++
 .../gcc.target/riscv/amo-table-a-6-load-2.c   |  17 ++
 .../gcc.target/riscv/amo-table-a-6-load-3.c   |  18 ++
 .../gcc.target/riscv/amo-table-a-6-store-1.c  |  16 ++
 .../gcc.target/riscv/amo-table-a-6-store-2.c  |  17 ++
 .../riscv/amo-table-a-6-store-compat-3.c      |  18 ++
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |   9 +
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |   9 +
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |   9 +
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |   9 +
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |   9 +
 gcc/testsuite/gcc.target/riscv/pr89835.c      |   9 +
 libgcc/config/riscv/atomic.c                  |   4 +-
 33 files changed, 563 insertions(+), 75 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c

Comments

Jakub Jelinek July 25, 2023, 7:50 p.m. UTC | #1 
On Tue, Jul 25, 2023 at 11:01:54AM -0700, Patrick O'Neill wrote:
> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
> Jeff Law.
> If there aren't any objections I'll commit this cherry-picked series
> on Thursday (July 27th).

Please don't before 13.2 will be released, the branch is frozen and none of
this seems to be a release blocker.

	Jakub
Palmer Dabbelt July 25, 2023, 7:58 p.m. UTC | #2 
On Tue, 25 Jul 2023 11:01:54 PDT (-0700), Patrick O'Neill wrote:
> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
> Jeff Law.
> If there aren't any objections I'll commit this cherry-picked series
> on Thursday (July 27th).

+Jakub

According to the "GCC 13.1.1 Status Report (2023-07-20)", it looks like 
we're frozen for 13.2 and thus would need a release maintainer to sign 
off on anything we backport until 13.2 is released.

I'm not opposed to the backport, but it does looks like we're down to no 
P1 regressions which means we might release very soon.  So we should at 
least make sure this gets through all the tests and such.  It's kind of 
splitting hairs as this is a pretty bad set of bugs we're fixing and 
distros are probably going to just backport it anyway, so not sure what 
the right answer is.

> Patchset on trunk:
> https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/
> First commit: f37a36bce81b50a43ec1613c1d08d803642f7506
>
> Also includes bugfix from:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109713
> commit: 4bd434fbfc7865961a8e10d7e9601b28765ce7be
>
> [1] https://inbox.sourceware.org/gcc/mhng-b7423fca-67ec-4ce4-9694-4e062632ceb0@palmer-ri-x1c9/T/#t
>
> Martin Liska (1):
>   riscv: fix error: control reaches end of non-void function
>
> Patrick O'Neill (11):
>   RISC-V: Eliminate SYNC memory models
>   RISC-V: Enforce Libatomic LR/SC SEQ_CST
>   RISC-V: Enforce subword atomic LR/SC SEQ_CST
>   RISC-V: Enforce atomic compare_exchange SEQ_CST
>   RISC-V: Add AMO release bits
>   RISC-V: Strengthen atomic stores
>   RISC-V: Eliminate AMO op fences
>   RISC-V: Weaken LR/SC pairs
>   RISC-V: Weaken mem_thread_fence
>   RISC-V: Weaken atomic loads
>   RISC-V: Table A.6 conformance tests
>
>  gcc/config/riscv/riscv-protos.h               |   3 +
>  gcc/config/riscv/riscv.cc                     |  66 ++++--
>  gcc/config/riscv/sync.md                      | 196 ++++++++++++------
>  .../riscv/amo-table-a-6-amo-add-1.c           |  15 ++
>  .../riscv/amo-table-a-6-amo-add-2.c           |  15 ++
>  .../riscv/amo-table-a-6-amo-add-3.c           |  15 ++
>  .../riscv/amo-table-a-6-amo-add-4.c           |  15 ++
>  .../riscv/amo-table-a-6-amo-add-5.c           |  15 ++
>  .../riscv/amo-table-a-6-compare-exchange-1.c  |   9 +
>  .../riscv/amo-table-a-6-compare-exchange-2.c  |   9 +
>  .../riscv/amo-table-a-6-compare-exchange-3.c  |   9 +
>  .../riscv/amo-table-a-6-compare-exchange-4.c  |   9 +
>  .../riscv/amo-table-a-6-compare-exchange-5.c  |   9 +
>  .../riscv/amo-table-a-6-compare-exchange-6.c  |  10 +
>  .../riscv/amo-table-a-6-compare-exchange-7.c  |   9 +
>  .../gcc.target/riscv/amo-table-a-6-fence-1.c  |  14 ++
>  .../gcc.target/riscv/amo-table-a-6-fence-2.c  |  15 ++
>  .../gcc.target/riscv/amo-table-a-6-fence-3.c  |  15 ++
>  .../gcc.target/riscv/amo-table-a-6-fence-4.c  |  15 ++
>  .../gcc.target/riscv/amo-table-a-6-fence-5.c  |  15 ++
>  .../gcc.target/riscv/amo-table-a-6-load-1.c   |  16 ++
>  .../gcc.target/riscv/amo-table-a-6-load-2.c   |  17 ++
>  .../gcc.target/riscv/amo-table-a-6-load-3.c   |  18 ++
>  .../gcc.target/riscv/amo-table-a-6-store-1.c  |  16 ++
>  .../gcc.target/riscv/amo-table-a-6-store-2.c  |  17 ++
>  .../riscv/amo-table-a-6-store-compat-3.c      |  18 ++
>  .../riscv/amo-table-a-6-subword-amo-add-1.c   |   9 +
>  .../riscv/amo-table-a-6-subword-amo-add-2.c   |   9 +
>  .../riscv/amo-table-a-6-subword-amo-add-3.c   |   9 +
>  .../riscv/amo-table-a-6-subword-amo-add-4.c   |   9 +
>  .../riscv/amo-table-a-6-subword-amo-add-5.c   |   9 +
>  gcc/testsuite/gcc.target/riscv/pr89835.c      |   9 +
>  libgcc/config/riscv/atomic.c                  |   4 +-
>  33 files changed, 563 insertions(+), 75 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c
Palmer Dabbelt July 25, 2023, 8:01 p.m. UTC | #3 
On Tue, 25 Jul 2023 12:50:48 PDT (-0700), jakub@redhat.com wrote:
> On Tue, Jul 25, 2023 at 11:01:54AM -0700, Patrick O'Neill wrote:
>> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
>> Jeff Law.
>> If there aren't any objections I'll commit this cherry-picked series
>> on Thursday (July 27th).
>
> Please don't before 13.2 will be released, the branch is frozen and none of
> this seems to be a release blocker.

Sorry I missed this.  IMO it's fine to wait, this has been broken for 
5-10 years so we can wait another cycle ;)

>
> 	Jakub
Jeff Law July 25, 2023, 9:02 p.m. UTC | #4 
On 7/25/23 13:50, Jakub Jelinek wrote:
> On Tue, Jul 25, 2023 at 11:01:54AM -0700, Patrick O'Neill wrote:
>> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
>> Jeff Law.
>> If there aren't any objections I'll commit this cherry-picked series
>> on Thursday (July 27th).
> 
> Please don't before 13.2 will be released, the branch is frozen and none of
> this seems to be a release blocker.
Ugh.  Missed the boat :(

I could make an argument for inclusion given the strong desire to have 
compatible mappings across the toolchains and alignment with the RVI 
specs -- but I won't.  As Palmer has indicated, it's been broken for a 
while and we can manage that breakage.




jeff
Palmer Dabbelt July 25, 2023, 9:16 p.m. UTC | #5 
On Tue, 25 Jul 2023 14:02:24 PDT (-0700), jeffreyalaw@gmail.com wrote:
>
>
> On 7/25/23 13:50, Jakub Jelinek wrote:
>> On Tue, Jul 25, 2023 at 11:01:54AM -0700, Patrick O'Neill wrote:
>>> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
>>> Jeff Law.
>>> If there aren't any objections I'll commit this cherry-picked series
>>> on Thursday (July 27th).
>>
>> Please don't before 13.2 will be released, the branch is frozen and none of
>> this seems to be a release blocker.
> Ugh.  Missed the boat :(
>
> I could make an argument for inclusion given the strong desire to have
> compatible mappings across the toolchains and alignment with the RVI
> specs -- but I won't.  As Palmer has indicated, it's been broken for a
> while and we can manage that breakage.

I think if we just merge it right after 13.2 and indicate that distros 
doing long-term binary builds before 13.3 backport the patches we should 
be fine.  I think that's just Debian right now, so while it's an 
important set of bugs to get fixed it's just the single user.

It's certainly a bummer to miss 13.2, but we've just got ourselves to 
blame for forgetting about the backport ;)

>
>
>
>
> jeff
Patrick O'Neill July 31, 2023, 4:19 p.m. UTC | #6 
GCC 13.2 released[2] so I merged the series now that the branch is unfrozen.

Thanks,
Patrick

[2] https://inbox.sourceware.org/gcc/ZMJeq%2FY5SN+7i8a+@tucnak/T/#u

On 7/25/23 11:01, Patrick O'Neill wrote:
> Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
> Jeff Law.
> If there aren't any objections I'll commit this cherry-picked series
> on Thursday (July 27th).
>
> Patchset on trunk:
> https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/
> First commit: f37a36bce81b50a43ec1613c1d08d803642f7506
>
> Also includes bugfix from:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109713
> commit: 4bd434fbfc7865961a8e10d7e9601b28765ce7be
>
> [1] https://inbox.sourceware.org/gcc/mhng-b7423fca-67ec-4ce4-9694-4e062632ceb0@palmer-ri-x1c9/T/#t
>
> Martin Liska (1):
>    riscv: fix error: control reaches end of non-void function
>
> Patrick O'Neill (11):
>    RISC-V: Eliminate SYNC memory models
>    RISC-V: Enforce Libatomic LR/SC SEQ_CST
>    RISC-V: Enforce subword atomic LR/SC SEQ_CST
>    RISC-V: Enforce atomic compare_exchange SEQ_CST
>    RISC-V: Add AMO release bits
>    RISC-V: Strengthen atomic stores
>    RISC-V: Eliminate AMO op fences
>    RISC-V: Weaken LR/SC pairs
>    RISC-V: Weaken mem_thread_fence
>    RISC-V: Weaken atomic loads
>    RISC-V: Table A.6 conformance tests
>
>   gcc/config/riscv/riscv-protos.h               |   3 +
>   gcc/config/riscv/riscv.cc                     |  66 ++++--
>   gcc/config/riscv/sync.md                      | 196 ++++++++++++------
>   .../riscv/amo-table-a-6-amo-add-1.c           |  15 ++
>   .../riscv/amo-table-a-6-amo-add-2.c           |  15 ++
>   .../riscv/amo-table-a-6-amo-add-3.c           |  15 ++
>   .../riscv/amo-table-a-6-amo-add-4.c           |  15 ++
>   .../riscv/amo-table-a-6-amo-add-5.c           |  15 ++
>   .../riscv/amo-table-a-6-compare-exchange-1.c  |   9 +
>   .../riscv/amo-table-a-6-compare-exchange-2.c  |   9 +
>   .../riscv/amo-table-a-6-compare-exchange-3.c  |   9 +
>   .../riscv/amo-table-a-6-compare-exchange-4.c  |   9 +
>   .../riscv/amo-table-a-6-compare-exchange-5.c  |   9 +
>   .../riscv/amo-table-a-6-compare-exchange-6.c  |  10 +
>   .../riscv/amo-table-a-6-compare-exchange-7.c  |   9 +
>   .../gcc.target/riscv/amo-table-a-6-fence-1.c  |  14 ++
>   .../gcc.target/riscv/amo-table-a-6-fence-2.c  |  15 ++
>   .../gcc.target/riscv/amo-table-a-6-fence-3.c  |  15 ++
>   .../gcc.target/riscv/amo-table-a-6-fence-4.c  |  15 ++
>   .../gcc.target/riscv/amo-table-a-6-fence-5.c  |  15 ++
>   .../gcc.target/riscv/amo-table-a-6-load-1.c   |  16 ++
>   .../gcc.target/riscv/amo-table-a-6-load-2.c   |  17 ++
>   .../gcc.target/riscv/amo-table-a-6-load-3.c   |  18 ++
>   .../gcc.target/riscv/amo-table-a-6-store-1.c  |  16 ++
>   .../gcc.target/riscv/amo-table-a-6-store-2.c  |  17 ++
>   .../riscv/amo-table-a-6-store-compat-3.c      |  18 ++
>   .../riscv/amo-table-a-6-subword-amo-add-1.c   |   9 +
>   .../riscv/amo-table-a-6-subword-amo-add-2.c   |   9 +
>   .../riscv/amo-table-a-6-subword-amo-add-3.c   |   9 +
>   .../riscv/amo-table-a-6-subword-amo-add-4.c   |   9 +
>   .../riscv/amo-table-a-6-subword-amo-add-5.c   |   9 +
>   gcc/testsuite/gcc.target/riscv/pr89835.c      |   9 +
>   libgcc/config/riscv/atomic.c                  |   4 +-
>   33 files changed, 563 insertions(+), 75 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
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