Message ID | 20230725180206.284777-6-patrick@rivosinc.com |
---|---|
State | New |
Headers | show
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Tue, 25 Jul 2023 11:02:30 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:29 -0700 (PDT) From: Patrick O'Neill <patrick@rivosinc.com> To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill <patrick@rivosinc.com> Subject: [gcc13 backport 05/12] RISC-V: Add AMO release bits Date: Tue, 25 Jul 2023 11:01:59 -0700 Message-Id: <20230725180206.284777-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> |
Series |
RISC-V: Implement ISA Manual Table A.6 Mappings
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expand
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 11b897aca5c..df55c427b1b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4498,8 +4498,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F':
This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)