@@ -33167,6 +33167,10 @@ rs6000_split_logical_inner (rtx dest,
if (complement_op2_p)
op2 = gen_rtx_NOT (mode, op2);
+ /* For canonical RTL, if only one arm is inverted it is the first. */
+ if (!complement_op1_p && complement_op2_p)
+ std::swap (op1, op2);
+
bool_rtx = ((code == NOT)
? gen_rtx_NOT (mode, op1)
: gen_rtx_fmt_ee (code, mode, op1, op2));
@@ -7570,8 +7570,8 @@ (define_insn_and_split "*boolc<mode>3_internal1"
[(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
(match_operator:BOOL_128 3 "boolean_operator"
[(not:BOOL_128
- (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
- (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
"TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
@@ -7586,7 +7586,7 @@ (define_insn_and_split "*boolc<mode>3_internal1"
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
DONE;
}
[(set (attr "type")
@@ -7607,14 +7607,14 @@ (define_insn_and_split "*boolc<mode>3_internal2"
[(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
(match_operator:TI2 3 "boolean_operator"
[(not:TI2
- (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
- (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
+ (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
+ (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
"!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
"#"
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
DONE;
}
[(set_attr "type" "integer")