From patchwork Sat Dec 20 15:18:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 423083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3361814009B for ; Sun, 21 Dec 2014 02:19:03 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=fpyf7hDri+qT 67Q7fwHqTjZpueet6zHq1pv51CJW1uiG8FS/w8ApEo6a7361osQTw1DMEnWAwcKh F4P2Dmh/ucNnbH+AyhoxRcuAWHf+8YtiVK+0NCVAE4SgX5bNzGZtcYMqZvWRt0JP j9AnSOqrmyhZmgNutGnJJdYE4zUEC2g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=xwQS+2cuM/nVNhweaG xcj44WRZ0=; b=miNvzQaNC+IR/M1VPiN22IAH6evhGzEIMZJfMl2tjdAr5pY0p4 Fth4l1XrmiYh54R9tNy2BhwzbQriLjv7gxcVfgL5G0/3F6HEWEHSmFTi+FutoyHz 9YCyVTW11FYh/jqKThcs+A2zyUuZYY5DkpNupDIx/2vzXQ0+46ygmer7U= Received: (qmail 16789 invoked by alias); 20 Dec 2014 15:18:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16774 invoked by uid 89); 20 Dec 2014 15:18:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sat, 20 Dec 2014 15:18:50 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id sBKFImGP049013; Sat, 20 Dec 2014 07:18:48 -0800 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id sBKFIhaX048968; Sat, 20 Dec 2014 07:18:43 -0800 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool , Pat Haugen Subject: [PATCH] rs6000: Make rs6000_split_logical handle inverted 2nd operand (PR64358) Date: Sat, 20 Dec 2014 07:18:40 -0800 Message-Id: <026b6a6be3c17513aedc8272f4fd6942e6db0b92.1419087240.git.segher@kernel.crashing.org> X-IsSubscribed: yes If rs6000_split_logical is asked to invert the second operand (but not the first), it emits RTL that is just that; but canonical RTL has the first arm inverted if only one, not the second. This patch fixes that. With that in place, the bug in PR target/64358 is easily fixed. Do that. Also change the other 128-bit boolc splitter to have the same operand order as everything else. And use BOOL_REGS_OP1 and _OP2 for operands 1 resp. 2 (not the other way around); this doesn't actually matter, but it was a bit confusing. This fixes builtin-arith-overflow-{10,11}.c as well. Bootstrapped (no fortran this time, it doesn't build right now) and tested on powerpc64-linux, -m32,-m32/-mpowerpc64,-m64,-m64/-mlra; no regressions (and the mentioned cases fixed). Okay for mainline? Does this need backporting as well? Segher 2014-12-20 Segher Boessenkool gcc/ PR target/64358 * config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the input operands if only the second is inverted. * config/rs6000/rs6000.md (*boolc3_internal1 for BOOL_128): Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to rs6000_split_logical. (*boolc3_internal2 for TI2): Swap operands[1] and operands[2]. --- gcc/config/rs6000/rs6000.c | 4 ++++ gcc/config/rs6000/rs6000.md | 12 ++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 73152ce..bbed888 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -33167,6 +33167,10 @@ rs6000_split_logical_inner (rtx dest, if (complement_op2_p) op2 = gen_rtx_NOT (mode, op2); + /* For canonical RTL, if only one arm is inverted it is the first. */ + if (!complement_op1_p && complement_op2_p) + std::swap (op1, op2); + bool_rtx = ((code == NOT) ? gen_rtx_NOT (mode, op1) : gen_rtx_fmt_ee (code, mode, op1, op2)); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 36e6182..2d3a5d3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7570,8 +7570,8 @@ (define_insn_and_split "*boolc3_internal1" [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") (match_operator:BOOL_128 3 "boolean_operator" [(not:BOOL_128 - (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")]))] + (match_operand:BOOL_128 2 "vlogical_operand" "")) + (match_operand:BOOL_128 1 "vlogical_operand" "")]))] "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" { if (TARGET_VSX && vsx_register_operand (operands[0], mode)) @@ -7586,7 +7586,7 @@ (define_insn_and_split "*boolc3_internal1" && reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true); DONE; } [(set (attr "type") @@ -7607,14 +7607,14 @@ (define_insn_and_split "*boolc3_internal2" [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") (match_operator:TI2 3 "boolean_operator" [(not:TI2 - (match_operand:TI2 1 "int_reg_operand" "r,0,r")) - (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))] + (match_operand:TI2 2 "int_reg_operand" "r,0,r")) + (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))] "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" "#" "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true); DONE; } [(set_attr "type" "integer")