[1/2] ARM: tegra: Correct Tegra30 SMMU register map

Correct Tegra30 SMMU register map.

Signed-off-by: Mark Zhang <markz@nvidia.com>
---
 arch/arm/boot/dts/tegra30.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

On 11/06/2013 08:58 PM, Mark Zhang wrote:
> Correct Tegra30 SMMU register map.

Some more explanation is required here re: why this layout is more
correct than what's there.

Do you need to edit the reg property in Tegra30's memory-controller node
too; that's what all these reg ranges are interleaved with, so
presumably if there was a mistake in the SMMU ranges, there's the
equivalent inverse mistake in the MC's ranges?

The DT binding for nvidia,tegra30-smmu states that reg should include
precisely 3 entries. This patch no longer conforms to that. The binding
needs to be re-written to explain the interleaving issue, and say that
an arbitrary number of ranges may be provided. The same issue exists in
the nvidia,tegra30-mc DT binding.

I think I'm beginning to regret separating out the MC and SMMU into
separate DT nodes:-(
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Hiroshi has mentioned that the TRM should be revised. :)
Because there are some registers which are needed by SMMU driver while
they're not in TRM yet.

So this patch doesn't make sense now. Thanks for the review.

Mark
On 11/13/2013 03:19 AM, Stephen Warren wrote:
> On 11/06/2013 08:58 PM, Mark Zhang wrote:
>> Correct Tegra30 SMMU register map.
> 
> Some more explanation is required here re: why this layout is more
> correct than what's there.
> 
> Do you need to edit the reg property in Tegra30's memory-controller node
> too; that's what all these reg ranges are interleaved with, so
> presumably if there was a mistake in the SMMU ranges, there's the
> equivalent inverse mistake in the MC's ranges?
> 
> The DT binding for nvidia,tegra30-smmu states that reg should include
> precisely 3 entries. This patch no longer conforms to that. The binding
> needs to be re-written to explain the interleaving issue, and say that
> an arbitrary number of ranges may be provided. The same issue exists in
> the nvidia,tegra30-mc DT binding.
> 
> I think I'm beginning to regret separating out the MC and SMMU into
> separate DT nodes:-(
> 
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

On Tue, 12 Nov 2013 20:19:04 +0100
Stephen Warren <swarren@wwwdotorg.org> wrote:

> On 11/06/2013 08:58 PM, Mark Zhang wrote:
> > Correct Tegra30 SMMU register map.
> 
> Some more explanation is required here re: why this layout is more
> correct than what's there.
> 
> Do you need to edit the reg property in Tegra30's memory-controller node
> too; that's what all these reg ranges are interleaved with, so
> presumably if there was a mistake in the SMMU ranges, there's the
> equivalent inverse mistake in the MC's ranges?
> 
> The DT binding for nvidia,tegra30-smmu states that reg should include
> precisely 3 entries. This patch no longer conforms to that. The binding
> needs to be re-written to explain the interleaving issue, and say that
> an arbitrary number of ranges may be provided. The same issue exists in
> the nvidia,tegra30-mc DT binding.
> 
> I think I'm beginning to regret separating out the MC and SMMU into
> separate DT nodes:-(

What's difficult is that how to handle the undocumented register area.
If we get rid of undocumented/reserved register area, then the number
of banks in SMMU/MC would increase unnecessarily. But practically we
can handle MC/SMMU multi register banks by just identifying MC/SMMU
portion with checking undocumented ones.
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html