From patchwork Thu Nov 7 03:58:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 289178 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 877F32C0336 for ; Thu, 7 Nov 2013 14:59:22 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752856Ab3KGD7V (ORCPT ); Wed, 6 Nov 2013 22:59:21 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19460 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752686Ab3KGD7V (ORCPT ); Wed, 6 Nov 2013 22:59:21 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 06 Nov 2013 19:58:35 -0800 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 06 Nov 2013 19:53:59 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 06 Nov 2013 19:53:59 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.327.1; Wed, 6 Nov 2013 19:59:20 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.712.24; Wed, 6 Nov 2013 19:59:20 -0800 Received: from hkemhub02.nvidia.com (10.18.67.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.712.24 via Frontend Transport; Wed, 6 Nov 2013 19:59:20 -0800 Received: from markz-hp6200.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.327.1; Thu, 7 Nov 2013 11:58:56 +0800 From: Mark Zhang To: , CC: , Mark Zhang Subject: [PATCH 1/2] ARM: tegra: Correct Tegra30 SMMU register map Date: Thu, 7 Nov 2013 11:58:25 +0800 Message-ID: <1383796706-10729-2-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1383796706-10729-1-git-send-email-markz@nvidia.com> References: <1383796706-10729-1-git-send-email-markz@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Correct Tegra30 SMMU register map. Signed-off-by: Mark Zhang --- arch/arm/boot/dts/tegra30.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cfd88ad..5f56243cc3f5 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -527,9 +527,12 @@ iommu { compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; + reg = <0x7000f010 0x014 + 0x7000f030 0x00c + 0x7000f228 0x00c + 0x7000f238 0x024 + 0x7000f264 0x010 + 0x7000f278 0x00c>; nvidia,#asids = <4>; /* # of ASIDs */ dma-window = <0 0x40000000>; /* IOVA start & length */ nvidia,ahb = <&ahb>;