diff mbox series

[33/33] target/mips: Adjust style in msa_translate_init()

Message ID	20211023214803.522078-34-f4bug@amsat.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PATCH 33/33] target/mips: Adjust style in msa_translate_init() Date: Sat, 23 Oct 2021 23:48:03 +0200 Message-Id: <20211023214803.522078-34-f4bug@amsat.org> In-Reply-To: <20211023214803.522078-1-f4bug@amsat.org> References: <20211023214803.522078-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Luis Pires <luis.pires@eldorado.org.br>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/mips: Fully convert MSA opcodes to decodetree \| expand [00/33] target/mips: Fully convert MSA opcodes to decodetree [01/33] tests/tcg: Fix some targets default cross compiler path [02/33] target/mips: Fix MSA MADDV.B opcode [03/33] target/mips: Fix MSA MSUBV.B opcode [04/33] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation [05/33] target/mips: Have check_msa_access() return a boolean [06/33] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum [07/33] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v [08/33] target/mips: Convert MSA LDI opcode to decodetree [09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers [10/33] target/mips: Extract df_extract() helper [11/33] target/mips: Convert MSA I5 instruction format to decodetree [12/33] target/mips: Convert MSA BIT instruction format to decodetree [13/33] target/mips: Convert MSA SHF opcode to decodetree [14/33] target/mips: Convert MSA I8 instruction format to decodetree [15/33] target/mips: Convert MSA load/store instruction format to decodetree [16/33] target/mips: Convert MSA 2RF instruction format to decodetree [17/33] target/mips: Convert MSA FILL opcode to decodetree [18/33] target/mips: Convert MSA 2R instruction format to decodetree [19/33] target/mips: Convert MSA VEC instruction format to decodetree [20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) [21/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) [22/33] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) [23/33] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) [24/33] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) [25/33] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) [26/33] target/mips: Convert MSA ELM instruction format to decodetree [27/33] target/mips: Convert MSA COPY_U opcode to decodetree [28/33] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree [29/33] target/mips: Convert MSA MOVE.V opcode to decodetree [30/33] target/mips: Convert CFCMSA and CTCMSA opcodes to decodetree [31/33] target/mips: Remove generic MSA opcode [32/33] target/mips: Remove one MSA unnecessary decodetree overlap group [33/33] target/mips: Adjust style in msa_translate_init()

Commit Message

Philippe Mathieu-Daudé Oct. 23, 2021, 9:48 p.m. UTC

While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Richard Henderson Oct. 24, 2021, 9:18 p.m. UTC | #1

On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
> While the first 'off' variable assignment is unused, it helps
> to better understand the code logic. Move the assignation where
> it would have been used so it is easier to compare the MSA
> registers based on FPU ones versus the MSA specific registers.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

diff mbox series

Patch

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5d8cad378e6..d196cad196b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -80,13 +80,15 @@  void msa_translate_init(void)
     int i;
 
     for (i = 0; i < 32; i++) {
-        int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+        int off;
 
         /*
          * The MSA vector registers are mapped on the
          * scalar floating-point unit (FPU) registers.
          */
+        off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
         msa_wr_d[i * 2] = fpu_f64[i];
+
         off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
         msa_wr_d[i * 2 + 1] =
                 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);