| Message ID | a2bf6f2d273169382f92923eb3293435d87a40f3.1610370064.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | 506009fc1022d5b883e95502e1c5dc38ac1da127 |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | [1/2] xilinx: common: Change macro handling in board_fdt_blob_setup() | expand |
po 11. 1. 2021 v 14:01 odesÃlatel Michal Simek <michal.simek@xilinx.com> napsal: > > Remove ifdef logic which is handled by preprocessor and move it link time > optimization to get full compile code coverage. > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > board/xilinx/common/board.c | 36 ++++++++++++++++++++---------------- > 1 file changed, 20 insertions(+), 16 deletions(-) > > diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c > index cdc06a39ce58..9f651db734c7 100644 > --- a/board/xilinx/common/board.c > +++ b/board/xilinx/common/board.c > @@ -324,25 +324,29 @@ void *board_fdt_blob_setup(void) > { > void *fdt_blob; > > -#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR) > - fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; > + if (!IS_ENABLED(CONFIG_VERSAL_NO_DDR) && > + !IS_ENABLED(CONFIG_VERSAL_NO_DDR)) { > + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; > > - if (fdt_magic(fdt_blob) == FDT_MAGIC) > - return fdt_blob; > + if (fdt_magic(fdt_blob) == FDT_MAGIC) > + return fdt_blob; > > - debug("DTB is not passed via %p\n", fdt_blob); > -#endif > + debug("DTB is not passed via %p\n", fdt_blob); > + } > > -#ifdef CONFIG_SPL_BUILD > - /* FDT is at end of BSS unless it is in a different memory region */ > - if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) > - fdt_blob = (ulong *)&_image_binary_end; > - else > - fdt_blob = (ulong *)&__bss_end; > -#else > - /* FDT is at end of image */ > - fdt_blob = (ulong *)&_end; > -#endif > + if (IS_ENABLED(CONFIG_SPL_BUILD)) { > + /* > + * FDT is at end of BSS unless it is in a different memory > + * region > + */ > + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) > + fdt_blob = (ulong *)&_image_binary_end; > + else > + fdt_blob = (ulong *)&__bss_end; > + } else { > + /* FDT is at end of image */ > + fdt_blob = (ulong *)&_end; > + } > > if (fdt_magic(fdt_blob) == FDT_MAGIC) > return fdt_blob; > -- > 2.30.0 > Applied. M
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index cdc06a39ce58..9f651db734c7 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -324,25 +324,29 @@ void *board_fdt_blob_setup(void) { void *fdt_blob; -#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR) - fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + if (!IS_ENABLED(CONFIG_VERSAL_NO_DDR) && + !IS_ENABLED(CONFIG_VERSAL_NO_DDR)) { + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; - if (fdt_magic(fdt_blob) == FDT_MAGIC) - return fdt_blob; + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; - debug("DTB is not passed via %p\n", fdt_blob); -#endif + debug("DTB is not passed via %p\n", fdt_blob); + } -#ifdef CONFIG_SPL_BUILD - /* FDT is at end of BSS unless it is in a different memory region */ - if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) - fdt_blob = (ulong *)&_image_binary_end; - else - fdt_blob = (ulong *)&__bss_end; -#else - /* FDT is at end of image */ - fdt_blob = (ulong *)&_end; -#endif + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + /* + * FDT is at end of BSS unless it is in a different memory + * region + */ + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) + fdt_blob = (ulong *)&_image_binary_end; + else + fdt_blob = (ulong *)&__bss_end; + } else { + /* FDT is at end of image */ + fdt_blob = (ulong *)&_end; + } if (fdt_magic(fdt_blob) == FDT_MAGIC) return fdt_blob;
Remove ifdef logic which is handled by preprocessor and move it link time optimization to get full compile code coverage. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- board/xilinx/common/board.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-)