| Message ID | 20201107140026.1974312-1-aford173@gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [V2,1/5] dt-bindings: add defines for i.MX8MN power domains | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success |
On Sat, Nov 07, 2020 at 08:00:23AM -0600, Adam Ford wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MN. There are more power domains, but the displaymix and mipi > power domains need a separate clock block controller which not yet > available, so this limits it to the HSIO, OTG and GPU domains. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > V2: Fix missing includes > Remove interrupt controller flag > Remove domains which interact with blk-ctl > > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 36 +++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Sat, Nov 07, 2020 at 08:00:24AM -0600, Adam Ford wrote: > The USB OTG controller cannot be used until the power-domain is enabled > unless it was started in the bootloader. > > Adding the power-domain reference to the OTG node allows the OTG > controller to operate. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > V2: No change > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Sat, Nov 07, 2020 at 08:00:25AM -0600, Adam Ford wrote: > According to the documentation from NXP, the i.MX8M Nano has a > Vivante GC7000 Ultra Lite as its GPU core. > > With this patch, the Etnaviv driver presents the GPU as: > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > The stock operating voltage for the i.MX8M Nano is .85V which means > the GPU needs to run at 400MHz. For boards where the operating > voltage is higher, this can be increased. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > V2: Move into this series > Update clocking description > > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 5e4b6934de40..6e650ea422a7 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1008,6 +1008,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, > + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE_DIV>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; It would be nice to align indentation here to <0> above. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Sat, Nov 07, 2020 at 08:00:22AM -0600, Adam Ford wrote: > This adds support for the power domains founds on i.MX8MN. The Nano > has fewer domains than the Mini, and the access to some of these domains > is different than that of the Mini, the Mini power domains cannot be > reused. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Acked-by: Krzysztof Kozlowski <krzk@kernel.org> It doesn't apply for me. Shawn
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index d3539569d45f..a87c44c15ace 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - fsl,imx7d-gpc + - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h new file mode 100644 index 000000000000..102ee85a9b62 --- /dev/null +++ b/include/dt-bindings/power/imx8mn-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Compass Electronics Group, LLC + */ + +#ifndef __DT_BINDINGS_IMX8MN_POWER_H__ +#define __DT_BINDINGS_IMX8MN_POWER_H__ + +#define IMX8MN_POWER_DOMAIN_HSIOMIX 0 +#define IMX8MN_POWER_DOMAIN_OTG1 1 +#define IMX8MN_POWER_DOMAIN_GPUMIX 2 +#define IMX8MN_POWER_DOMAIN_DISPMIX 3 +#define IMX8MN_POWER_DOMAIN_MIPI 4 + +#endif