| Message ID | 1517660564-22428-1-git-send-email-david.wu@rock-chips.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | Add integrated phy support for rk322x and rk3328 | expand |
> The gmac2phy is connected with integrated with phy, we can > fix the phy node at dtsi level. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Sat, 3 Feb 2018, David Wu wrote: > The gmac2phy is connected with integrated with phy, we can > fix the phy node at dtsi level. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > > arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi > index 5de1059..7026601 100644 > --- a/arch/arm/dts/rk3328.dtsi > +++ b/arch/arm/dts/rk3328.dtsi > @@ -475,6 +475,41 @@ > status = "disabled"; > }; > > + gmac2phy: ethernet@ff550000 { > + compatible = "rockchip,rk3328-gmac"; > + reg = <0x0 0xff550000 0x0 0x10000>; > + rockchip,grf = <&grf>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq"; > + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, > + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, > + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, > + <&cru SCLK_MAC2PHY_OUT>; > + clock-names = "stmmaceth", "mac_clk_rx", > + "mac_clk_tx", "clk_mac_ref", > + "aclk_mac", "pclk_mac", > + "clk_macphy"; > + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; > + reset-names = "stmmaceth", "mac-phy"; > + phy-mode = "rmii"; > + phy-handle = <&phy>; > + pinctrl-names = "default"; > + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; > + status = "disabled"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + phy: phy@0 { > + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + phy-is-integrated; Again: is this a common config option? If not: shouldn't this be "rockchip,phy-is-integrated"? > + }; > + }; > + }; > + > usb_host0_ehci: usb@ff5c0000 { > compatible = "generic-ehci"; > reg = <0x0 0xff5c0000 0x0 0x10000>; >
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 5de1059..7026601 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -475,6 +475,41 @@ status = "disabled"; }; + gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-is-integrated; + }; + }; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>;
The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level. Signed-off-by: David Wu <david.wu@rock-chips.com> --- arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)