diff mbox

[ARM] Fix failure in testsuite/gcc.c-torture/compile/sync-3.c

Message ID 000001cb49b1$80c515f0$824f41d0$@shawcroft@arm.com
State New
Headers show

Commit Message

Marcus Shawcroft Sept. 1, 2010, 8:41 a.m. UTC 
The sync-3.c test case failure occurs for ARM because the combiner changes
an indirect address into an indirect address with offset.  The load / store
exclusive instructions use the memory_operand predicate and 'm' constraint
but should use a predicate that allows only memory indirect and
corresponding constraint.

Regression run.

Cheers
/Marcus
2010-08-31  Marcus Shawcroft  <marcus.shawcroft@arm.com>

	* config/arm/predicates.md (arm_sync_memory_operand): New.
	* config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate
        to arm_sync_memory_operand and constraint to Q.
	(arm_sync_compare_and_swap<mode>): Likewise.
	(arm_sync_compare_and_swap<mode>): Likewise.
	(arm_sync_lock_test_and_setsi): Likewise.
	(arm_sync_lock_test_and_set<mode>): Likewise.
        (arm_sync_new_<sync_optab>si): Likewise.
        (arm_sync_new_nandsi): Likewise.
        (arm_sync_new_<sync_optab><mode>): Likewise.
        (arm_sync_new_nand<mode>): Likewise.
        (arm_sync_old_<sync_optab>si): Likewise.
        (arm_sync_old_nandsi): Likewise.
        (arm_sync_old_<sync_optab><mode>): Likewise.
        (arm_sync_old_nand<mode>): Likewise.

Comments

Richard Earnshaw Sept. 1, 2010, 2:58 p.m. UTC | #1 
On Wed, 2010-09-01 at 09:41 +0100, Marcus Shawcroft wrote:
> The sync-3.c test case failure occurs for ARM because the combiner changes
> an indirect address into an indirect address with offset.  The load / store
> exclusive instructions use the memory_operand predicate and 'm' constraint
> but should use a predicate that allows only memory indirect and
> corresponding constraint.
> 
> Regression run.
> 
> Cheers
> /Marcus

OK.

R.
diff mbox

Patch

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 5481708..781eeaf 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -610,3 +610,8 @@ 
 		(and (match_test "TARGET_32BIT")
 		     (match_operand 0 "arm_di_operand"))))
 
+;; True if the operand is memory reference suitable for a ldrex/strex.
+(define_predicate "arm_sync_memory_operand"
+  (and (match_operand 0 "memory_operand")
+       (match_code "reg" "0")))
+
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 7fd38d7..f942d1f 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -280,7 +280,7 @@ 
 (define_insn "arm_sync_compare_and_swapsi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI
-	  [(match_operand:SI 1 "memory_operand" "+m")
+	  [(match_operand:SI 1 "arm_sync_memory_operand" "+Q")
    	   (match_operand:SI 2 "s_register_operand" "r")
 	   (match_operand:SI 3 "s_register_operand" "r")]
 	  VUNSPEC_SYNC_COMPARE_AND_SWAP))
@@ -307,7 +307,7 @@ 
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (zero_extend:SI
 	  (unspec_volatile:NARROW
-	    [(match_operand:NARROW 1 "memory_operand" "+m")
+	    [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")
    	     (match_operand:SI 2 "s_register_operand" "r")
 	     (match_operand:SI 3 "s_register_operand" "r")]
 	    VUNSPEC_SYNC_COMPARE_AND_SWAP)))
@@ -332,7 +332,7 @@ 
 
 (define_insn "arm_sync_lock_test_and_setsi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
-        (match_operand:SI 1 "memory_operand" "+m"))
+        (match_operand:SI 1 "arm_sync_memory_operand" "+Q"))
    (set (match_dup 1)
         (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")]
 	                    VUNSPEC_SYNC_LOCK))
@@ -353,7 +353,7 @@ 
 
 (define_insn "arm_sync_lock_test_and_set<mode>"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
-        (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m")))
+        (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")))
    (set (match_dup 1)
         (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")]
 	                        VUNSPEC_SYNC_LOCK))
@@ -375,7 +375,7 @@ 
 (define_insn "arm_sync_new_<sync_optab>si"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(syncop:SI
-                               (match_operand:SI 1 "memory_operand" "+m")
+                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
                                (match_operand:SI 2 "s_register_operand" "r"))
 	                    ]
 	                    VUNSPEC_SYNC_NEW_OP))
@@ -400,7 +400,7 @@ 
 (define_insn "arm_sync_new_nandsi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(not:SI (and:SI
-                               (match_operand:SI 1 "memory_operand" "+m")
+                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
                                (match_operand:SI 2 "s_register_operand" "r")))
 	                    ]
 	                    VUNSPEC_SYNC_NEW_OP))
@@ -426,7 +426,7 @@ 
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(syncop:SI
                                (zero_extend:SI
-			         (match_operand:NARROW 1 "memory_operand" "+m"))
+			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
                                (match_operand:SI 2 "s_register_operand" "r"))
 	                    ]
 	                    VUNSPEC_SYNC_NEW_OP))
@@ -454,7 +454,7 @@ 
 	  [(not:SI
 	     (and:SI
                (zero_extend:SI	  
-	         (match_operand:NARROW 1 "memory_operand" "+m"))
+	         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
                (match_operand:SI 2 "s_register_operand" "r")))
 	  ] VUNSPEC_SYNC_NEW_OP))
    (set (match_dup 1)
@@ -478,7 +478,7 @@ 
 (define_insn "arm_sync_old_<sync_optab>si"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(syncop:SI
-                               (match_operand:SI 1 "memory_operand" "+m")
+                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
                                (match_operand:SI 2 "s_register_operand" "r"))
 	                    ]
 	                    VUNSPEC_SYNC_OLD_OP))
@@ -504,7 +504,7 @@ 
 (define_insn "arm_sync_old_nandsi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(not:SI (and:SI
-                               (match_operand:SI 1 "memory_operand" "+m")
+                               (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
                                (match_operand:SI 2 "s_register_operand" "r")))
 	                    ]
 	                    VUNSPEC_SYNC_OLD_OP))
@@ -531,7 +531,7 @@ 
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(syncop:SI
                                (zero_extend:SI
-			         (match_operand:NARROW 1 "memory_operand" "+m"))
+			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
                                (match_operand:SI 2 "s_register_operand" "r"))
 	                    ]
 	                    VUNSPEC_SYNC_OLD_OP))
@@ -558,7 +558,7 @@ 
   [(set (match_operand:SI 0 "s_register_operand" "=&r")
         (unspec_volatile:SI [(not:SI (and:SI
                                (zero_extend:SI
-			         (match_operand:NARROW 1 "memory_operand" "+m"))
+			         (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
                                (match_operand:SI 2 "s_register_operand" "r")))
 	                    ]
 	                    VUNSPEC_SYNC_OLD_OP))