From patchwork Wed Sep 1 08:41:42 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 63356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id E44E0B714A for ; Wed, 1 Sep 2010 18:42:05 +1000 (EST) Received: (qmail 15055 invoked by alias); 1 Sep 2010 08:42:03 -0000 Received: (qmail 15033 invoked by uid 22791); 1 Sep 2010 08:42:01 -0000 X-SWARE-Spam-Status: No, hits=0.9 required=5.0 tests=AWL, BAYES_20, MIME_QP_LONG_LINE, MSGID_MULTIPLE_AT, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (217.140.96.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 01 Sep 2010 08:41:50 +0000 Received: from cam-owa2.Emea.Arm.com (cam-owa2.emea.arm.com [10.1.105.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id o818e4F9002712 for ; Wed, 1 Sep 2010 09:40:04 +0100 (BST) Received: from e102573 ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Sep 2010 09:41:45 +0100 From: "Marcus Shawcroft" To: Subject: [PATCH, ARM] Fix failure in testsuite/gcc.c-torture/compile/sync-3.c Date: Wed, 1 Sep 2010 09:41:42 +0100 Message-ID: <000001cb49b1$80c515f0$824f41d0$@shawcroft@arm.com> MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The sync-3.c test case failure occurs for ARM because the combiner changes an indirect address into an indirect address with offset. The load / store exclusive instructions use the memory_operand predicate and 'm' constraint but should use a predicate that allows only memory indirect and corresponding constraint. Regression run. Cheers /Marcus 2010-08-31 Marcus Shawcroft * config/arm/predicates.md (arm_sync_memory_operand): New. * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate to arm_sync_memory_operand and constraint to Q. (arm_sync_compare_and_swap): Likewise. (arm_sync_compare_and_swap): Likewise. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_lock_test_and_set): Likewise. (arm_sync_new_si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_new_): Likewise. (arm_sync_new_nand): Likewise. (arm_sync_old_si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_old_): Likewise. (arm_sync_old_nand): Likewise. diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 5481708..781eeaf 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -610,3 +610,8 @@ (and (match_test "TARGET_32BIT") (match_operand 0 "arm_di_operand")))) +;; True if the operand is memory reference suitable for a ldrex/strex. +(define_predicate "arm_sync_memory_operand" + (and (match_operand 0 "memory_operand") + (match_code "reg" "0"))) + diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 7fd38d7..f942d1f 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -280,7 +280,7 @@ (define_insn "arm_sync_compare_and_swapsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "+m") + [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "s_register_operand" "r")] VUNSPEC_SYNC_COMPARE_AND_SWAP)) @@ -307,7 +307,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (zero_extend:SI (unspec_volatile:NARROW - [(match_operand:NARROW 1 "memory_operand" "+m") + [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "s_register_operand" "r")] VUNSPEC_SYNC_COMPARE_AND_SWAP))) @@ -332,7 +332,7 @@ (define_insn "arm_sync_lock_test_and_setsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") - (match_operand:SI 1 "memory_operand" "+m")) + (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) (set (match_dup 1) (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] VUNSPEC_SYNC_LOCK)) @@ -353,7 +353,7 @@ (define_insn "arm_sync_lock_test_and_set" [(set (match_operand:SI 0 "s_register_operand" "=&r") - (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) + (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) (set (match_dup 1) (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] VUNSPEC_SYNC_LOCK)) @@ -375,7 +375,7 @@ (define_insn "arm_sync_new_si" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_NEW_OP)) @@ -400,7 +400,7 @@ (define_insn "arm_sync_new_nandsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_NEW_OP)) @@ -426,7 +426,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_NEW_OP)) @@ -454,7 +454,7 @@ [(not:SI (and:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_NEW_OP)) (set (match_dup 1) @@ -478,7 +478,7 @@ (define_insn "arm_sync_old_si" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_OLD_OP)) @@ -504,7 +504,7 @@ (define_insn "arm_sync_old_nandsi" [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI - (match_operand:SI 1 "memory_operand" "+m") + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_OLD_OP)) @@ -531,7 +531,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(syncop:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r")) ] VUNSPEC_SYNC_OLD_OP)) @@ -558,7 +558,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r") (unspec_volatile:SI [(not:SI (and:SI (zero_extend:SI - (match_operand:NARROW 1 "memory_operand" "+m")) + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) (match_operand:SI 2 "s_register_operand" "r"))) ] VUNSPEC_SYNC_OLD_OP))