diff mbox

[U-Boot,RESPIN,v2,04/15] x86: queensbay: Correct Topcliff device irqs

Message ID BLU437-SMTP737F44F836416B09D5CF81BFA00@phx.gbl
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng June 23, 2015, 4:18 a.m. UTC 
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.

This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/dts/crownbay.dts | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Comments

Simon Glass June 24, 2015, 2:45 a.m. UTC | #1 
On 22 June 2015 at 22:18, Bin Meng <bmeng.cn@gmail.com> wrote:
> There are 4 usb ports on the Intel Crown Bay board, 2 of which are
> connected to Topcliff usb host 0 and the other 2 connected to usb
> host 1. USB devices inserted in the ports connected to usb host 1
> cannot get detected due to wrong IRQ assigned to the controller.
> Actually we need apply the PCI interrupt pin swizzling logic to all
> devices on the Topcliff chipset when configuring the PIRQ routing.
>
> This was observed on usb ports, but device 6 and 10 irqs are also
> wrong. Correct them all together.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/dts/crownbay.dts | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)

Applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 87ed0f4..b77c65a 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -180,29 +180,29 @@ 
 				 * Note on the Crown Bay board, Topcliff chipset
 				 * is connected to TunnelCreek PCIe port 0, so
 				 * its bus number is 1 for its PCIe port and 2
-				 * for its PCI devices per U-Boot currnet PCI
+				 * for its PCI devices per U-Boot current PCI
 				 * bus enumeration algorithm.
 				 */
 				PCI_BDF(1, 0, 0) INTA PIRQA
 				PCI_BDF(2, 0, 1) INTA PIRQA
 				PCI_BDF(2, 0, 2) INTA PIRQA
-				PCI_BDF(2, 2, 0) INTB PIRQB
-				PCI_BDF(2, 2, 1) INTB PIRQB
-				PCI_BDF(2, 2, 2) INTB PIRQB
-				PCI_BDF(2, 2, 3) INTB PIRQB
-				PCI_BDF(2, 2, 4) INTB PIRQB
+				PCI_BDF(2, 2, 0) INTB PIRQD
+				PCI_BDF(2, 2, 1) INTB PIRQD
+				PCI_BDF(2, 2, 2) INTB PIRQD
+				PCI_BDF(2, 2, 3) INTB PIRQD
+				PCI_BDF(2, 2, 4) INTB PIRQD
 				PCI_BDF(2, 4, 0) INTC PIRQC
 				PCI_BDF(2, 4, 1) INTC PIRQC
-				PCI_BDF(2, 6, 0) INTD PIRQD
+				PCI_BDF(2, 6, 0) INTD PIRQB
 				PCI_BDF(2, 8, 0) INTA PIRQA
 				PCI_BDF(2, 8, 1) INTA PIRQA
 				PCI_BDF(2, 8, 2) INTA PIRQA
 				PCI_BDF(2, 8, 3) INTA PIRQA
-				PCI_BDF(2, 10, 0) INTB PIRQB
-				PCI_BDF(2, 10, 1) INTB PIRQB
-				PCI_BDF(2, 10, 2) INTB PIRQB
-				PCI_BDF(2, 10, 3) INTB PIRQB
-				PCI_BDF(2, 10, 4) INTB PIRQB
+				PCI_BDF(2, 10, 0) INTB PIRQD
+				PCI_BDF(2, 10, 1) INTB PIRQD
+				PCI_BDF(2, 10, 2) INTB PIRQD
+				PCI_BDF(2, 10, 3) INTB PIRQD
+				PCI_BDF(2, 10, 4) INTB PIRQD
 				PCI_BDF(2, 12, 0) INTC PIRQC
 				PCI_BDF(2, 12, 1) INTC PIRQC
 				PCI_BDF(2, 12, 2) INTC PIRQC