| Message ID | 861a1c152b58b8c99bd56b083c13a138f10cfaeb.1602078045.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | e9284066958e906118b3fd71d7e81e9916b2c58a |
| Delegated to: | Michal Simek |
| Headers | show
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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id q3sm1526616edv.17.2020.10.07.06.40.58 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Oct 2020 06:40:59 -0700 (PDT) From: Michal Simek <michal.simek@xilinx.com> To: u-boot@lists.denx.de, git@xilinx.com Subject: [PATCH 4/4] arm64: zynqmp: Enable FPGA loading from SPL Date: Wed, 7 Oct 2020 15:40:48 +0200 Message-Id: <861a1c152b58b8c99bd56b083c13a138f10cfaeb.1602078045.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <cover.1602078045.git.michal.simek@xilinx.com> References: <cover.1602078045.git.michal.simek@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean |
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arm64: zynqmp: Enable loading FPGA by SPL
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diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index c54ddffdd6f3..79a0091b1981 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y
fpga bitstream needs to be listed in config node in FIT image. Only tested option is bitstream in BIN format. Enabling this feature increase code size by almost 4k. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+)