diff mbox series

[Agilex7,M-series,Platform,Enablement,v1,01/16] arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series

Message ID 20240517052701.12949-2-tingting.meng@intel.com
State Changes Requested
Delegated to: Tom Rini
Headers show
Series [Agilex7,M-series,Platform,Enablement,v1,01/16] arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series | expand

Commit Message

Meng, Tingting May 17, 2024, 5:26 a.m. UTC 
From: Wan Yee Lau <wan.yee.lau@intel.com>

Add Agilex7 M-series dtsi and dts for new platform Agilex7 M-series.

Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Signed-off-by: Tingting Meng <tingting.meng@intel.com>
---
 ...tsi => socfpga_agilex7m_socdk-u-boot.dtsi} |  37 ++++-
 ...x_socdk.dts => socfpga_agilex7m_socdk.dts} |  66 +++++++--
 arch/arm/dts/socfpga_soc64_u-boot.dtsi        | 127 ++++++++++++++++++
 3 files changed, 213 insertions(+), 17 deletions(-)
 copy arch/arm/dts/{socfpga_agilex_socdk-u-boot.dtsi => socfpga_agilex7m_socdk-u-boot.dtsi} (50%)
 copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_agilex7m_socdk.dts} (63%)
 create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi

Comments

Tom Rini May 17, 2024, 3:08 p.m. UTC | #1 
On Fri, May 17, 2024 at 01:26:46PM +0800, tingting.meng@intel.com wrote:

> From: Wan Yee Lau <wan.yee.lau@intel.com>
> 
> Add Agilex7 M-series dtsi and dts for new platform Agilex7 M-series.
> 
> Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
> Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
> Signed-off-by: Tingting Meng <tingting.meng@intel.com>
> ---
>  ...tsi => socfpga_agilex7m_socdk-u-boot.dtsi} |  37 ++++-
>  ...x_socdk.dts => socfpga_agilex7m_socdk.dts} |  66 +++++++--
>  arch/arm/dts/socfpga_soc64_u-boot.dtsi        | 127 ++++++++++++++++++
>  3 files changed, 213 insertions(+), 17 deletions(-)
>  copy arch/arm/dts/{socfpga_agilex_socdk-u-boot.dtsi => socfpga_agilex7m_socdk-u-boot.dtsi} (50%)
>  copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_agilex7m_socdk.dts} (63%)
>  create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi

Why can't we use OF_UPSTREAM on these platforms?
Meng, Tingting May 20, 2024, 8:36 a.m. UTC | #2 
> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Friday, May 17, 2024 11:08 PM
> To: Meng, Tingting <tingting.meng@intel.com>
> Cc: u-boot@lists.denx.de; Lukasz Majewski <lukma@denx.de>; Sean
> Anderson <seanga2@gmail.com>; Rayagonda Kokatanur
> <rayagonda.kokatanur@broadcom.com>; Marek <marex@denx.de>; Simon
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Hea, Kok Kiang <kok.kiang.hea@intel.com>;
> Maniyam, Dinesh <dinesh.maniyam@intel.com>; Ng, Boon Khai
> <boon.khai.ng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Chong, Teik Heng
> <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.zamri@intel.com>; Lim, Jit Loon
> <jit.loon.lim@intel.com>; Tang, Sieu Mun <sieu.mun.tang@intel.com>; Lau,
> Wan Yee <wan.yee.lau@intel.com>
> Subject: Re: [Agilex7 M-series Platform Enablement v1 01/16] arch: arm: dts:
> Add dts and dtsi for new platform Agilex7 M-series
> 
> On Fri, May 17, 2024 at 01:26:46PM +0800, tingting.meng@intel.com wrote:
> 
> > From: Wan Yee Lau <wan.yee.lau@intel.com>
> >
> > Add Agilex7 M-series dtsi and dts for new platform Agilex7 M-series.
> >
> > Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
> > Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
> > Signed-off-by: Tingting Meng <tingting.meng@intel.com>
> > ---
> >  ...tsi => socfpga_agilex7m_socdk-u-boot.dtsi} |  37 ++++-
> > ...x_socdk.dts => socfpga_agilex7m_socdk.dts} |  66 +++++++--
> >  arch/arm/dts/socfpga_soc64_u-boot.dtsi        | 127 ++++++++++++++++++
> >  3 files changed, 213 insertions(+), 17 deletions(-)  copy
> > arch/arm/dts/{socfpga_agilex_socdk-u-boot.dtsi =>
> > socfpga_agilex7m_socdk-u-boot.dtsi} (50%)  copy
> > arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_agilex7m_socdk.dts}
> > (63%)  create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
> 
> Why can't we use OF_UPSTREAM on these platforms?
> 
> --
> Tom
ok, Tom, will convert to OF_UPSTREAM
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
similarity index 50%
copy from arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
copy to arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
index 63df28e836..4369f0b545 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
@@ -2,12 +2,18 @@ 
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_agilex-u-boot.dtsi"
+#include "socfpga_soc64_u-boot.dtsi"
 
 /{
+	chosen {
+		stdout-path = "serial0:115200n8";
+		u-boot,spl-boot-order = &mmc;
+	};
+
 	aliases {
 		spi0 = &qspi;
 		i2c0 = &i2c1;
@@ -23,9 +29,7 @@ 
 	};
 
 	memory {
-		/* 8GB */
-		reg = <0 0x00000000 0 0x80000000>,
-		      <2 0x80000000 1 0x80000000>;
+		reg = <0 0x00000000 0 0x80000000>;
 	};
 };
 
@@ -34,22 +38,43 @@ 
 	spi-tx-bus-width = <4>;
 	spi-rx-bus-width = <4>;
 	bootph-all;
+	/delete-property/ cdns,read-delay;
 };
 
 &i2c1 {
 	status = "okay";
 };
 
+&nand {
+	status = "okay";
+	nand-bus-width = <16>;
+	bootph-all;
+};
+
 &mmc {
 	drvsel = <3>;
 	smplsel = <0>;
 	bootph-all;
 };
 
-&qspi {
-	status = "okay";
+&sdr {
+	compatible = "intel,sdr-ctl-agilex7m";
+
+	reg = <0xf8020000 0x100>;
+};
+
+&socfpga_l3interconnect_firewall {
+	soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+		intel,offset-settings =
+			/* Disable MPFE firewall for SMMU */
+			<0x00000000 0x00010101 0x00010101>;
+	};
 };
 
 &watchdog0 {
 	bootph-all;
 };
+
+&binman {
+	/delete-node/ kernel;
+};
diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex7m_socdk.dts
similarity index 63%
copy from arch/arm/dts/socfpga_agilex_socdk.dts
copy to arch/arm/dts/socfpga_agilex7m_socdk.dts
index bcdeecc0e0..ba929b9c74 100644
--- a/arch/arm/dts/socfpga_agilex_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex7m_socdk.dts
@@ -1,11 +1,11 @@ 
 // SPDX-License-Identifier:     GPL-2.0
 /*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2024, Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
 
 / {
-	model = "SoCFPGA Agilex SoCDK";
+	model = "SoCFPGA Agilex7-M SoCDK";
 
 	aliases {
 		serial0 = &uart0;
@@ -14,10 +14,6 @@ 
 		ethernet2 = &gmac2;
 	};
 
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	leds {
 		compatible = "gpio-leds";
 		hps0 {
@@ -85,6 +81,36 @@ 
 	};
 };
 
+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <3800>;
+
+	mdio2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy2: ethernet-phy@2 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <1860>; /* 960ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
 &mmc {
 	status = "okay";
 	cap-sd-highspeed;
@@ -128,13 +154,31 @@ 
 			#size-cells = <1>;
 
 			qspi_boot: partition@0 {
-				label = "Boot and fpga data";
-				reg = <0x0 0x034B0000>;
+				label = "u-boot";
+				reg = <0x0 0x04200000>;
+			};
+
+			root: partition@4200000 {
+				label = "root";
+				reg = <0x04200000 0x0BE00000>;
 			};
+		};
+	};
+};
 
-			qspi_rootfs: partition@34B0000 {
-				label = "Root Filesystem - JFFS2";
-				reg = <0x034B0000 0x0EB50000>;
+&nand {
+	flash@0 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "u-boot";
+				reg = <0 0x200000>;
+			};
+			partition@200000 {
+				label = "root";
+				reg = <0x200000 0x3fe00000>;
 			};
 		};
 	};
diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
new file mode 100644
index 0000000000..d8a121ade8
--- /dev/null
+++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
@@ -0,0 +1,127 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+/ {
+	soc {
+		socfpga-system-mgr-firewall {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			i_sys_mgr_core@ffd12000 {
+				reg = <0xffd12000 0x00000230>;
+				intel,offset-settings =
+					/* Enable non-secure interface to DMA */
+					<0x00000020 0xff010000 0xff010011>,
+					/* Enable non-secure interface to DMA periph */
+					<0x00000024 0xffffffff 0xffffffff>;
+				bootph-all;
+			};
+		};
+
+		socfpga_l3interconnect_firewall:socfpga-l3interconnect-firewall {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			noc_fw_l4_per_l4_per_scr@ffd21000 {
+				reg = <0xffd21000 0x00000074>;
+				intel,offset-settings =
+					/* Disable L4 periphs firewall */
+					<0x00000000 0x01010001 0x01010001>,
+					<0x00000004 0x01010001 0x01010001>,
+					<0x0000000c 0x01010001 0x01010001>,
+					<0x00000010 0x01010001 0x01010001>,
+					<0x0000001c 0x01010001 0x01010101>,
+					<0x00000020 0x01010001 0x01010101>,
+					<0x00000024 0x01010001 0x01010101>,
+					<0x00000028 0x01010001 0x01010101>,
+					<0x0000002c 0x01010001 0x01010001>,
+					<0x00000030 0x01010001 0x01010001>,
+					<0x00000034 0x01010001 0x01010001>,
+					<0x00000040 0x01010001 0x01010001>,
+					<0x00000044 0x01010001 0x01010101>,
+					<0x00000048 0x01010001 0x01010101>,
+					<0x00000050 0x01010001 0x01010101>,
+					<0x00000054 0x01010001 0x01010101>,
+					<0x00000058 0x01010001 0x01010101>,
+					<0x0000005c 0x01010001 0x01010101>,
+					<0x00000060 0x01010001 0x01010101>,
+					<0x00000064 0x01010001 0x01010101>,
+					<0x00000068 0x01010001 0x01010101>,
+					<0x0000006c 0x01010001 0x01010101>,
+					<0x00000070 0x01010001 0x01010101>;
+				bootph-all;
+			};
+
+			noc_fw_l4_sys_l4_sys_scr@ffd21100 {
+				reg = <0xffd21100 0x00000098>;
+				intel,offset-settings =
+					/* Disable L4 system firewall */
+					<0x00000008 0x01010001 0x01010001>,
+					<0x0000000c 0x01010001 0x01010001>,
+					<0x00000010 0x01010001 0x01010001>,
+					<0x00000014 0x01010001 0x01010001>,
+					<0x00000018 0x01010001 0x01010001>,
+					<0x0000001c 0x01010001 0x01010001>,
+					<0x00000020 0x01010001 0x01010001>,
+					<0x0000002c 0x01010001 0x01010001>,
+					<0x00000030 0x01010001 0x01010001>,
+					<0x00000034 0x01010001 0x01010001>,
+					<0x00000038 0x01010001 0x01010001>,
+					<0x00000040 0x01010001 0x01010001>,
+					<0x00000044 0x01010001 0x01010001>,
+					<0x00000048 0x01010001 0x01010001>,
+					<0x0000004c 0x01010001 0x01010001>,
+					<0x00000054 0x01010001 0x01010001>,
+					<0x00000058 0x01010001 0x01010001>,
+					<0x0000005c 0x01010001 0x01010001>,
+					<0x00000060 0x01010001 0x01010101>,
+					<0x00000064 0x01010001 0x01010101>,
+					<0x00000068 0x01010001 0x01010101>,
+					<0x0000006c 0x01010001 0x01010101>,
+					<0x00000070 0x01010001 0x01010101>,
+					<0x00000074 0x01010001 0x01010101>,
+					<0x00000078 0x01010001 0x03010001>,
+					<0x00000090 0x01010001 0x01010001>,
+					<0x00000094 0x01010001 0x01010001>;
+				bootph-all;
+			};
+
+			noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
+				reg = <0xffd21200 0x00000004>;
+				/* Disable soc2fpga security access */
+				intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+				bootph-all;
+			};
+
+			noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
+				reg = <0xffd21300 0x00000004>;
+				/* Disable lightweight soc2fpga security access */
+				intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+				bootph-all;
+			};
+
+			noc_fw_tcu_tcu_scr@ffd21400 {
+				reg = <0xffd21400 0x00000004>;
+				/* Disable DMA ECC security access, for SMMU use */
+				intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
+				bootph-all;
+			};
+
+			noc_fw_priv_MemoryMap_priv@ffd24800 {
+				reg = <0xffd24800 0x0000000c>;
+				intel,offset-settings =
+				/* Enable non-prviledged access to various periphs */
+					<0x00000000 0xfff73ffb 0xfff73ffb>;
+				bootph-all;
+			};
+		};
+	};
+};