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[v1,1/2] arm: dts: k3-am625-verdin: Update autogenerated LPDDR4 configuration

Message ID 20240515080058.1530985-2-ghidoliemanuele@gmail.com
State Accepted
Delegated to: Tom Rini
Headers show
Series arm: dts: k3-am625-verdin: Enable LPDDR4 WDQS control | expand

Commit Message

Emanuele Ghidoli May 15, 2024, 8 a.m. UTC 
From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

Update the autogenerated LPDDR4 configuration using the latest available
SysConfig tool.
This changes are cosmetic and are made to track the last used tool version.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
---
 arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 841541bb2433..ca883ae82c7d 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
- * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.10.01
+ * Tue May 14 2024 12:55:28 GMT+0200 (Central European Summer Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 800MHz
  * Density (per channel): 16Gb
@@ -10,9 +10,11 @@ 
  * Number of Ranks: 1
 */
 
+
 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
 
 
 #define DDRSS_CTL_0_DATA 0x00000B00