| Message ID | 20240320090214.40465-7-ada@thorsis.com |
|---|---|
| State | Superseded |
| Delegated to: | Dario Binacchi |
| Headers | show |
| Series | mtd: nand: raw: Collected improvements | expand |
Hi Alex, ------------------------------------------ Override the ONFI timing mode at runtime. Signed-off-by: Alexander Dahl <ada@thorsis.com> --- Tested-by: Mihai Sain <mihai.sain@microchip.com> I tested your new command on a new board/soc sam9x75-curiosity 😊 I find it very very useful ! I also rounded the master clock to 270 MHz 😊 Thanks. => nand info Device 0: nand0, sector size 256 KiB Manufacturer MACRONIX Model MX30LF4G28AD Device size 512 MiB Page size 4096 b OOB size 256 b Erase size 262144 b ecc strength 8 bits ecc step size 512 b subpagesize 4096 b options 0x40004200 bbt options 0x00028000 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x00000004 SMC_PULSE2: 0x0c070d05 SMC_CYCLE2: 0x000c000d SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns) NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns) NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns) NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 2 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x00000003 SMC_PULSE2: 0x0e090e06 SMC_CYCLE2: 0x000e000e SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns) NRD: setup: 0 (0 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 14 (42 ns) NCS_WR: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns) NWE: setup: 3 (9 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 14 (42 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 1 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x00000003 SMC_PULSE2: 0x110a1109 SMC_CYCLE2: 0x00110011 SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns) NRD: setup: 0 (0 ns), pulse: 10 (30 ns), hold: 7 (21 ns), cycle: 17 (51 ns) NCS_WR: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns) NWE: setup: 3 (9 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 17 (51 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand onfi 3 => hsmc decode MCK rate: 270 MHz SMC_SETUP2: 0x00000004 SMC_PULSE2: 0x0c070d05 SMC_CYCLE2: 0x000c000d SMC_MODE2: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns) NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns) NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns) NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns) Standard read applied TDF optimization enabled TDF cycles: 15 (45 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal => nand torture 0x800000 0x800000 NAND torture: device 0 offset 0x800000 size 0x800000 (block size 0x40000) Passed: 32, failed: 0 => clk dump 24000000 1 | |-- mainck 1080000000 1 | | |-- plla_fracck 1080000000 1 | | | |-- plla_divpmcck 1080000000 1 | | | | `-- mck_pres 270000000 8 | | | | `-- mck_div Best regards, Mihai Sain
Hi Alex,
--------------------------------------------------------
Override the ONFI timing mode at runtime.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
I used the same board sam9x75-curiosity to test mode 5 😊
I forced in nfc driver the mode 5:
+ if (conf->timings.sdr.tRC_min < 20000)
And I ran the nand torture on 16 MiB:
=> nand onfi 0
=> hsmc decode
MCK rate: 270 MHz
SMC_SETUP2: 0x00000007
SMC_PULSE2: 0x22112211
SMC_CYCLE2: 0x00220022
SMC_MODE2: 0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 ns)
NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns)
NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal
=> time nand torture 0x800000 0x1000000
NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
Passed: 64, failed: 0
time: 30.152 seconds
=> nand onfi 5
=> hsmc decode
MCK rate: 270 MHz
SMC_SETUP2: 0x00000001
SMC_PULSE2: 0x0b060804
SMC_CYCLE2: 0x000b0008
SMC_MODE2: 0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns)
NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns)
NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns)
NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal
=> time nand torture 0x800000 0x1000000
NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000)
Passed: 64, failed: 0
time: 15.891 seconds
Best regards,
Mihai Sain
Hi I think this command can be really useful. On Wed, Mar 20, 2024 at 3:09 PM <Mihai.Sain@microchip.com> wrote: > > Hi Alex, > > -------------------------------------------------------- > > Override the ONFI timing mode at runtime. > > Signed-off-by: Alexander Dahl <ada@thorsis.com> > --- > > I used the same board sam9x75-curiosity to test mode 5 😊 > > I forced in nfc driver the mode 5: > + if (conf->timings.sdr.tRC_min < 20000) > > And I ran the nand torture on 16 MiB: > > => nand onfi 0 > => hsmc decode > > MCK rate: 270 MHz > > SMC_SETUP2: 0x00000007 > SMC_PULSE2: 0x22112211 > SMC_CYCLE2: 0x00220022 > SMC_MODE2: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns) > NRD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 17 (51 ns), cycle: 34 (102 ns) > NCS_WR: setup: 0 (0 ns), pulse: 34 (102 ns), hold: 0 (0 ns), cycle: 34 (102 ns) > NWE: setup: 7 (21 ns), pulse: 17 (51 ns), hold: 10 (30 ns), cycle: 34 (102 ns) > Standard read applied > TDF optimization enabled > TDF cycles: 15 (45 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > > => time nand torture 0x800000 0x1000000 > > NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000) > Passed: 64, failed: 0 > > time: 30.152 seconds > > => nand onfi 5 > => hsmc decode > > MCK rate: 270 MHz > > SMC_SETUP2: 0x00000001 > SMC_PULSE2: 0x0b060804 > SMC_CYCLE2: 0x000b0008 > SMC_MODE2: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 11 (33 ns), hold: 0 (0 ns), cycle: 11 (33 ns) > NRD: setup: 0 (0 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 11 (33 ns) > NCS_WR: setup: 0 (0 ns), pulse: 8 (24 ns), hold: 0 (0 ns), cycle: 8 (24 ns) > NWE: setup: 1 (3 ns), pulse: 4 (12 ns), hold: 3 (9 ns), cycle: 8 (24 ns) > Standard read applied > TDF optimization enabled > TDF cycles: 15 (45 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > > => time nand torture 0x800000 0x1000000 > > NAND torture: device 0 offset 0x800000 size 0x1000000 (block size 0x40000) > Passed: 64, failed: 0 > > time: 15.891 seconds > Let try to have more testing on more boards Michael > Best regards, > Mihai Sain
Hi Michael, ------------------------------------------------------- I think this command can be really useful. Let try to have more testing on more boards --------------------------------------------------------- I managed to test the command on sama7g54-curiosity board. I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000). => nand onfi 0 => hsmc decode MCK rate: 200 MHz HSMC_SETUP3: 0x00000004 HSMC_PULSE3: 0x140a140a HSMC_CYCLE3: 0x00140014 HSMC_TIMINGS3: 0x880805f4 HSMC_MODE3: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) TDF optimization enabled TDF cycles: 15 (75 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal NFSEL (NAND Flash Selection) is set OCMS (Off Chip Memory Scrambling) is disabled TWB (WEN High to REN to Busy): 64 (320 ns) TRR (Ready to REN Low Delay): 64 (320 ns) TAR (ALE to REN Low Delay): 5 (25 ns) TADL (ALE to Data Start): 71 (355 ns) TCLR (CLE to REN Low Delay): 4 (20 ns) => time nand torture 0x1000000 0x1000000 NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) Passed: 64, failed: 0 time: 22.638 seconds => nand onfi 5 => hsmc decode MCK rate: 200 MHz HSMC_SETUP3: 0x00000001 HSMC_PULSE3: 0x07040502 HSMC_CYCLE3: 0x00070005 HSMC_TIMINGS3: 0x880402f2 HSMC_MODE3: 0x001f0003 NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) TDF optimization enabled TDF cycles: 15 (75 ns) Data Bus Width: 8-bit bus NWAIT Mode: 0 Write operation controlled by NWE signal Read operation controlled by NRD signal NFSEL (NAND Flash Selection) is set OCMS (Off Chip Memory Scrambling) is disabled TWB (WEN High to REN to Busy): 64 (320 ns) TRR (Ready to REN Low Delay): 4 (20 ns) TAR (ALE to REN Low Delay): 2 (10 ns) TADL (ALE to Data Start): 71 (355 ns) TCLR (CLE to REN Low Delay): 2 (10 ns) => time nand torture 0x1000000 0x1000000 NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) Passed: 64, failed: 0 time: 11.661 seconds => nand info Device 0: nand0, sector size 256 KiB Manufacturer MACRONIX Model MX30LF4G28AD Device size 512 MiB Page size 4096 b OOB size 256 b Erase size 262144 b ecc strength 8 bits ecc step size 512 b subpagesize 4096 b options 0x40004200 bbt options 0x00028000 Best regards, Mihai Sain
Hello Mihai, Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com: > Hi Michael, > > ------------------------------------------------------- > > I think this command can be really useful. > Let try to have more testing on more boards > > --------------------------------------------------------- > > I managed to test the command on sama7g54-curiosity board. Thanks for that. Nice to see it works on other variants of the SoC family. > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000). You did a similar thing for the sam9x75. These boards/socs seem to have a newer SMC / HSMC controller than sama5d2 or sam9x60? The driver claims all the (H)SMC incarnations do _not_ support these EDO modes 4 and 5. Maybe someone could have a deeper look at the datasheets of the newer SoCs and propose a patch to support those newer controllers in the atmel nand-controller driver? I guess the problem is the same in Linux, right? Greets Alex > > => nand onfi 0 > => hsmc decode > > MCK rate: 200 MHz > > HSMC_SETUP3: 0x00000004 > HSMC_PULSE3: 0x140a140a > HSMC_CYCLE3: 0x00140014 > HSMC_TIMINGS3: 0x880805f4 > HSMC_MODE3: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) > TDF optimization enabled > TDF cycles: 15 (75 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > NFSEL (NAND Flash Selection) is set > OCMS (Off Chip Memory Scrambling) is disabled > TWB (WEN High to REN to Busy): 64 (320 ns) > TRR (Ready to REN Low Delay): 64 (320 ns) > TAR (ALE to REN Low Delay): 5 (25 ns) > TADL (ALE to Data Start): 71 (355 ns) > TCLR (CLE to REN Low Delay): 4 (20 ns) > > => time nand torture 0x1000000 0x1000000 > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > Passed: 64, failed: 0 > > time: 22.638 seconds > > => nand onfi 5 > => hsmc decode > > MCK rate: 200 MHz > > HSMC_SETUP3: 0x00000001 > HSMC_PULSE3: 0x07040502 > HSMC_CYCLE3: 0x00070005 > HSMC_TIMINGS3: 0x880402f2 > HSMC_MODE3: 0x001f0003 > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) > NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > TDF optimization enabled > TDF cycles: 15 (75 ns) > Data Bus Width: 8-bit bus > NWAIT Mode: 0 > Write operation controlled by NWE signal > Read operation controlled by NRD signal > NFSEL (NAND Flash Selection) is set > OCMS (Off Chip Memory Scrambling) is disabled > TWB (WEN High to REN to Busy): 64 (320 ns) > TRR (Ready to REN Low Delay): 4 (20 ns) > TAR (ALE to REN Low Delay): 2 (10 ns) > TADL (ALE to Data Start): 71 (355 ns) > TCLR (CLE to REN Low Delay): 2 (10 ns) > > => time nand torture 0x1000000 0x1000000 > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > Passed: 64, failed: 0 > > time: 11.661 seconds > > => nand info > > Device 0: nand0, sector size 256 KiB > Manufacturer MACRONIX > Model MX30LF4G28AD > Device size 512 MiB > Page size 4096 b > OOB size 256 b > Erase size 262144 b > ecc strength 8 bits > ecc step size 512 b > subpagesize 4096 b > options 0x40004200 > bbt options 0x00028000 > > Best regards, > Mihai Sain
HI On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote: > > Hello Mihai, > > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com: > > Hi Michael, > > > > ------------------------------------------------------- > > > > I think this command can be really useful. > > Let try to have more testing on more boards > > > > --------------------------------------------------------- > > > > I managed to test the command on sama7g54-curiosity board. > > Thanks for that. Nice to see it works on other variants of the SoC > family. > > > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000). > > You did a similar thing for the sam9x75. These boards/socs seem to > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > driver claims all the (H)SMC incarnations do _not_ support these EDO > modes 4 and 5. Maybe someone could have a deeper look at the > datasheets of the newer SoCs and propose a patch to support those > newer controllers in the atmel nand-controller driver? I guess the > problem is the same in Linux, right? > > Greets > Alex > > > > > => nand onfi 0 > > => hsmc decode > > > > MCK rate: 200 MHz > > > > HSMC_SETUP3: 0x00000004 > > HSMC_PULSE3: 0x140a140a > > HSMC_CYCLE3: 0x00140014 > > HSMC_TIMINGS3: 0x880805f4 > > HSMC_MODE3: 0x001f0003 > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) > > TDF optimization enabled > > TDF cycles: 15 (75 ns) > > Data Bus Width: 8-bit bus > > NWAIT Mode: 0 > > Write operation controlled by NWE signal > > Read operation controlled by NRD signal > > NFSEL (NAND Flash Selection) is set > > OCMS (Off Chip Memory Scrambling) is disabled > > TWB (WEN High to REN to Busy): 64 (320 ns) > > TRR (Ready to REN Low Delay): 64 (320 ns) > > TAR (ALE to REN Low Delay): 5 (25 ns) > > TADL (ALE to Data Start): 71 (355 ns) > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > => time nand torture 0x1000000 0x1000000 > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > Passed: 64, failed: 0 > > > > time: 22.638 seconds > > > > => nand onfi 5 > > => hsmc decode > > > > MCK rate: 200 MHz > > > > HSMC_SETUP3: 0x00000001 > > HSMC_PULSE3: 0x07040502 > > HSMC_CYCLE3: 0x00070005 > > HSMC_TIMINGS3: 0x880402f2 > > HSMC_MODE3: 0x001f0003 > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) > > NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > > TDF optimization enabled > > TDF cycles: 15 (75 ns) > > Data Bus Width: 8-bit bus > > NWAIT Mode: 0 > > Write operation controlled by NWE signal > > Read operation controlled by NRD signal > > NFSEL (NAND Flash Selection) is set > > OCMS (Off Chip Memory Scrambling) is disabled > > TWB (WEN High to REN to Busy): 64 (320 ns) > > TRR (Ready to REN Low Delay): 4 (20 ns) > > TAR (ALE to REN Low Delay): 2 (10 ns) > > TADL (ALE to Data Start): 71 (355 ns) > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > => time nand torture 0x1000000 0x1000000 > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > Passed: 64, failed: 0 > > > > time: 11.661 seconds > > > > => nand info > > > > Device 0: nand0, sector size 256 KiB > > Manufacturer MACRONIX > > Model MX30LF4G28AD > > Device size 512 MiB > > Page size 4096 b > > OOB size 256 b > > Erase size 262144 b > > ecc strength 8 bits > > ecc step size 512 b > > subpagesize 4096 b > > options 0x40004200 > > bbt options 0x00028000 > > > > Best regards, > > Mihai Sain I'm in favor to have it even cover by one soc family. I would like to confirm on imx6 and imx8. If you are not in a rush. Let's us test too Michael
Hello Michael, Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi: > HI > > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote: > > > > Hello Mihai, > > > > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com: > > > Hi Michael, > > > > > > ------------------------------------------------------- > > > > > > I think this command can be really useful. > > > Let try to have more testing on more boards > > > > > > --------------------------------------------------------- > > > > > > I managed to test the command on sama7g54-curiosity board. > > > > Thanks for that. Nice to see it works on other variants of the SoC > > family. > > > > > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000). > > > > You did a similar thing for the sam9x75. These boards/socs seem to > > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > > driver claims all the (H)SMC incarnations do _not_ support these EDO > > modes 4 and 5. Maybe someone could have a deeper look at the > > datasheets of the newer SoCs and propose a patch to support those > > newer controllers in the atmel nand-controller driver? I guess the > > problem is the same in Linux, right? > > > > Greets > > Alex > > > > > > > > => nand onfi 0 > > > => hsmc decode > > > > > > MCK rate: 200 MHz > > > > > > HSMC_SETUP3: 0x00000004 > > > HSMC_PULSE3: 0x140a140a > > > HSMC_CYCLE3: 0x00140014 > > > HSMC_TIMINGS3: 0x880805f4 > > > HSMC_MODE3: 0x001f0003 > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > > NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > > NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) > > > TDF optimization enabled > > > TDF cycles: 15 (75 ns) > > > Data Bus Width: 8-bit bus > > > NWAIT Mode: 0 > > > Write operation controlled by NWE signal > > > Read operation controlled by NRD signal > > > NFSEL (NAND Flash Selection) is set > > > OCMS (Off Chip Memory Scrambling) is disabled > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > TRR (Ready to REN Low Delay): 64 (320 ns) > > > TAR (ALE to REN Low Delay): 5 (25 ns) > > > TADL (ALE to Data Start): 71 (355 ns) > > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > > Passed: 64, failed: 0 > > > > > > time: 22.638 seconds > > > > > > => nand onfi 5 > > > => hsmc decode > > > > > > MCK rate: 200 MHz > > > > > > HSMC_SETUP3: 0x00000001 > > > HSMC_PULSE3: 0x07040502 > > > HSMC_CYCLE3: 0x00070005 > > > HSMC_TIMINGS3: 0x880402f2 > > > HSMC_MODE3: 0x001f0003 > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > > > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) > > > NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > > > TDF optimization enabled > > > TDF cycles: 15 (75 ns) > > > Data Bus Width: 8-bit bus > > > NWAIT Mode: 0 > > > Write operation controlled by NWE signal > > > Read operation controlled by NRD signal > > > NFSEL (NAND Flash Selection) is set > > > OCMS (Off Chip Memory Scrambling) is disabled > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > TRR (Ready to REN Low Delay): 4 (20 ns) > > > TAR (ALE to REN Low Delay): 2 (10 ns) > > > TADL (ALE to Data Start): 71 (355 ns) > > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > > Passed: 64, failed: 0 > > > > > > time: 11.661 seconds > > > > > > => nand info > > > > > > Device 0: nand0, sector size 256 KiB > > > Manufacturer MACRONIX > > > Model MX30LF4G28AD > > > Device size 512 MiB > > > Page size 4096 b > > > OOB size 256 b > > > Erase size 262144 b > > > ecc strength 8 bits > > > ecc step size 512 b > > > subpagesize 4096 b > > > options 0x40004200 > > > bbt options 0x00028000 > > > > > > Best regards, > > > Mihai Sain > > I'm in favor to have it even cover by one soc family. I would like to > confirm on imx6 and imx8. If you are not in a rush. > Let's us test too Agreed. This is a generic nand command, so it would of course be reasonable to test it on multiple nand controllers. I'm afraid I currently have only at91 boards on my desk for which I have a recent U-Boot _and_ a NAND chip soldered. So take your time for this patch. If you don't mind I would be happy if you could merge the four trivial patches which do not add new features and which already got your reviewed-by in the next cycle already, and let those other patches with the new subcommands for debugging be tested as long as needed. Kind regards Alex > > Michael > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > michael@amarulasolutions.com > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > info@amarulasolutions.com > www.amarulasolutions.com
HI On Fri, Mar 22, 2024 at 1:02 PM Alexander Dahl <ada@thorsis.com> wrote: > > Hello Michael, > > Am Fri, Mar 22, 2024 at 12:54:27PM +0100 schrieb Michael Nazzareno Trimarchi: > > HI > > > > On Fri, Mar 22, 2024 at 12:46 PM Alexander Dahl <ada@thorsis.com> wrote: > > > > > > Hello Mihai, > > > > > > Am Fri, Mar 22, 2024 at 10:02:29AM +0000 schrieb Mihai.Sain@microchip.com: > > > > Hi Michael, > > > > > > > > ------------------------------------------------------- > > > > > > > > I think this command can be really useful. > > > > Let try to have more testing on more boards > > > > > > > > --------------------------------------------------------- > > > > > > > > I managed to test the command on sama7g54-curiosity board. > > > > > > Thanks for that. Nice to see it works on other variants of the SoC > > > family. > > > > > > > I also forced timing mode 5 from controller driver (conf->timings.sdr.tRC_min < 20000). > > > > > > You did a similar thing for the sam9x75. These boards/socs seem to > > > have a newer SMC / HSMC controller than sama5d2 or sam9x60? The > > > driver claims all the (H)SMC incarnations do _not_ support these EDO > > > modes 4 and 5. Maybe someone could have a deeper look at the > > > datasheets of the newer SoCs and propose a patch to support those > > > newer controllers in the atmel nand-controller driver? I guess the > > > problem is the same in Linux, right? > > > > > > Greets > > > Alex > > > > > > > > > > > => nand onfi 0 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3: 0x00000004 > > > > HSMC_PULSE3: 0x140a140a > > > > HSMC_CYCLE3: 0x00140014 > > > > HSMC_TIMINGS3: 0x880805f4 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > > > NRD: setup: 0 (0 ns), pulse: 10 (50 ns), hold: 10 (50 ns), cycle: 20 (100 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 20 (100 ns), hold: 0 (0 ns), cycle: 20 (100 ns) > > > > NWE: setup: 4 (20 ns), pulse: 10 (50 ns), hold: 6 (30 ns), cycle: 20 (100 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 64 (320 ns) > > > > TAR (ALE to REN Low Delay): 5 (25 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 4 (20 ns) > > > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > > > Passed: 64, failed: 0 > > > > > > > > time: 22.638 seconds > > > > > > > > => nand onfi 5 > > > > => hsmc decode > > > > > > > > MCK rate: 200 MHz > > > > > > > > HSMC_SETUP3: 0x00000001 > > > > HSMC_PULSE3: 0x07040502 > > > > HSMC_CYCLE3: 0x00070005 > > > > HSMC_TIMINGS3: 0x880402f2 > > > > HSMC_MODE3: 0x001f0003 > > > > NCS_RD: setup: 0 (0 ns), pulse: 7 (35 ns), hold: 0 (0 ns), cycle: 7 (35 ns) > > > > NRD: setup: 0 (0 ns), pulse: 4 (20 ns), hold: 3 (15 ns), cycle: 7 (35 ns) > > > > NCS_WR: setup: 0 (0 ns), pulse: 5 (25 ns), hold: 0 (0 ns), cycle: 5 (25 ns) > > > > NWE: setup: 1 (5 ns), pulse: 2 (10 ns), hold: 2 (10 ns), cycle: 5 (25 ns) > > > > TDF optimization enabled > > > > TDF cycles: 15 (75 ns) > > > > Data Bus Width: 8-bit bus > > > > NWAIT Mode: 0 > > > > Write operation controlled by NWE signal > > > > Read operation controlled by NRD signal > > > > NFSEL (NAND Flash Selection) is set > > > > OCMS (Off Chip Memory Scrambling) is disabled > > > > TWB (WEN High to REN to Busy): 64 (320 ns) > > > > TRR (Ready to REN Low Delay): 4 (20 ns) > > > > TAR (ALE to REN Low Delay): 2 (10 ns) > > > > TADL (ALE to Data Start): 71 (355 ns) > > > > TCLR (CLE to REN Low Delay): 2 (10 ns) > > > > > > > > => time nand torture 0x1000000 0x1000000 > > > > > > > > NAND torture: device 0 offset 0x1000000 size 0x1000000 (block size 0x40000) > > > > Passed: 64, failed: 0 > > > > > > > > time: 11.661 seconds > > > > > > > > => nand info > > > > > > > > Device 0: nand0, sector size 256 KiB > > > > Manufacturer MACRONIX > > > > Model MX30LF4G28AD > > > > Device size 512 MiB > > > > Page size 4096 b > > > > OOB size 256 b > > > > Erase size 262144 b > > > > ecc strength 8 bits > > > > ecc step size 512 b > > > > subpagesize 4096 b > > > > options 0x40004200 > > > > bbt options 0x00028000 > > > > > > > > Best regards, > > > > Mihai Sain > > > > I'm in favor to have it even cover by one soc family. I would like to > > confirm on imx6 and imx8. If you are not in a rush. > > Let's us test too > > Agreed. This is a generic nand command, so it would of course be > reasonable to test it on multiple nand controllers. I'm afraid I > currently have only at91 boards on my desk for which I have a recent > U-Boot _and_ a NAND chip soldered. So take your time for this patch. > > If you don't mind I would be happy if you could merge the four trivial > patches which do not add new features and which already got your > reviewed-by in the next cycle already, and let those other patches > with the new subcommands for debugging be tested as long as needed. > I think Dario already queue them Michael > Kind regards > Alex > > > > > Michael > > > > -- > > Michael Nazzareno Trimarchi > > Co-Founder & Chief Executive Officer > > M. +39 347 913 2170 > > michael@amarulasolutions.com > > __________________________________ > > > > Amarula Solutions BV > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > > T. +31 (0)85 111 9172 > > info@amarulasolutions.com > > www.amarulasolutions.com
diff --git a/cmd/Kconfig b/cmd/Kconfig index 61e280fb1a4..c39cc297306 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1421,6 +1421,7 @@ config CMD_NAND NAND support. if CMD_NAND + config CMD_NAND_TRIMFFS bool "nand write.trimffs" default y if ARCH_SUNXI @@ -1437,6 +1438,15 @@ config CMD_NAND_TORTURE help NAND torture support. +config CMD_NAND_ONFI + bool "nand onfi" + help + Set ONFI timing modes explicitly. + This is a debugging command to switch to slower ONFI timing + modes for testing. + In normal operation determining the timing mode automatically + should work fine, and you don't need this. + endif # CMD_NAND config CMD_NVME diff --git a/cmd/nand.c b/cmd/nand.c index fe834c4ac5c..2b83a5ad1b8 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -494,6 +494,48 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev) } } +#ifdef CONFIG_CMD_NAND_ONFI +static int do_nand_onfi(struct mtd_info *mtd, int mode) +{ + struct nand_chip *chip; + int ret; + int i; + + if (mtd->type != MTD_NANDFLASH) { + printf("MTD device is no NAND flash!\n"); + return CMD_RET_FAILURE; + } + + chip = mtd_to_nand(mtd); + + if (mode < 0) { + printf("Reporting current ONFI settings not yet supported!\n"); + return CMD_RET_FAILURE; + } + + ret = onfi_init_data_interface(chip, chip->data_interface, + NAND_SDR_IFACE, mode); + if (ret) { + printf("onfi_init_data_interface() for mode %d failed with error %d\n", + mode, ret); + return CMD_RET_FAILURE; + } + + for (i = 0; i < chip->numchips; i++) { + chip->select_chip(mtd, i); + ret = nand_setup_data_interface(chip, i); + chip->select_chip(mtd, -1); + if (ret) { + printf("nand_setup_data_interface() for mode %d failed with error %d\n", + mode, ret); + return CMD_RET_FAILURE; + } + } + + return CMD_RET_SUCCESS; +} +#endif + static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -919,6 +961,21 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, } #endif +#ifdef CONFIG_CMD_NAND_ONFI + /* + * Syntax is: + * 0 1 2 + * nand onfi [mode] + */ + if (strcmp(cmd, "onfi") == 0) { + int mode = -1; + + if (argc > 2) + mode = dectoul(argv[2], NULL); + return do_nand_onfi(mtd, mode); + } +#endif + usage: return CMD_RET_USAGE; } @@ -961,6 +1018,10 @@ U_BOOT_LONGHELP(nand, " bring nand to lock state or display locked pages\n" "nand unlock[.allexcept] [offset] [size] - unlock section" #endif +#ifdef CONFIG_CMD_NAND_ONFI + "\n" + "nand onfi [mode] - set ONFI mode\n" +#endif #ifdef CONFIG_ENV_OFFSET_OOB "\n" "nand env.oob - environment offset in OOB of block 0 of" diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 688d17ba3c2..2384425a746 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -983,7 +983,7 @@ static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip) * * Returns 0 for success or negative error code otherwise. */ -static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) +int nand_setup_data_interface(struct nand_chip *chip, int chipnr) { struct mtd_info *mtd = nand_to_mtd(chip); int ret; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 4abaf4734cf..07bc4cc9051 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1315,6 +1315,7 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); uint8_t nand_read_byte(struct mtd_info *mtd); +int nand_setup_data_interface(struct nand_chip *chip, int chipnr); /* get timing characteristics from ONFI timing mode. */ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
Override the ONFI timing mode at runtime. Signed-off-by: Alexander Dahl <ada@thorsis.com> --- Notes: v2: - initial patch version (not present in v1) cmd/Kconfig | 10 ++++++ cmd/nand.c | 61 ++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/nand_base.c | 2 +- include/linux/mtd/rawnand.h | 1 + 4 files changed, 73 insertions(+), 1 deletion(-)