@@ -43,8 +43,9 @@ struct msm_sdhc_plat {
struct msm_sdhc {
struct sdhci_host host;
void *base;
+ struct clk_bulk clks;
};
struct msm_sdhc_variant_info {
bool mci_removed;
@@ -53,37 +54,59 @@ struct msm_sdhc_variant_info {
DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
{
- int node = dev_of_offset(dev);
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
- 400000);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
- struct clk clk;
- int ret;
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ ulong clk_rate;
+ int ret, i = 0, n_clks;
+ const char *clk_name;
- ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
+ ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate));
if (ret)
- return ret;
+ clk_rate = 400000;
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
- if (ret)
+ ret = clk_get_bulk(dev, &prv->clks);
+ if (ret) {
+ log_warning("Couldn't get mmc clocks: %d\n", ret);
return ret;
+ }
- clk.id = clkd[1];
- ret = clk_request(clk_dev, &clk);
- if (ret < 0)
+ ret = clk_enable_bulk(&prv->clks);
+ if (ret) {
+ log_warning("Couldn't enable mmc clocks: %d\n", ret);
return ret;
+ }
- ret = clk_set_rate(&clk, clk_rate);
- if (ret < 0)
- return ret;
+ /* If clock-names is unspecified, then the first clock is the core clock */
+ if (!ofnode_get_property(node, "clock-names", &n_clks)) {
+ if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
+ log_warning("Couldn't set core clock rate: %d\n", ret);
+ return -EINVAL;
+ }
+ }
+
+ /* Find the index of the "core" clock */
+ while (i < n_clks) {
+ ofnode_read_string_index(node, "clock-names", i, &clk_name);
+ if (!strcmp(clk_name, "core"))
+ break;
+ i++;
+ }
+
+ if (i >= prv->clks.count) {
+ log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
+ prv->clks.count);
+ return -EINVAL;
+ }
+
+ /* The clock is already enabled by the clk_bulk above */
+ clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate);
+ /* If we get a rate of 0 then something has probably gone wrong. */
+ if (clk_rate == 0 || IS_ERR((void *)clk_rate)) {
+ log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0);
+ return -EINVAL;
+ }
return 0;
}
@@ -186,8 +209,10 @@ static int msm_sdc_remove(struct udevice *dev)
/* Disable host-controller mode */
if (!var_info->mci_removed)
writel(0, priv->base + SDCC_MCI_HC_MODE);
+ clk_release_bulk(&priv->clks);
+
return 0;
}
static int msm_of_to_plat(struct udevice *dev)