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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id bt1-20020a056000080100b0033d9c7eb63csm9142256wrb.84.2024.02.26.09.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 09:26:24 -0800 (PST) From: Caleb Connolly Date: Mon, 26 Feb 2024 17:26:07 +0000 Subject: [PATCH v5 03/39] mmc: msm_sdhci: use modern clock handling MIME-Version: 1.0 Message-Id: <20240226-b4-qcom-common-target-v5-3-10c8e078befb@linaro.org> References: <20240226-b4-qcom-common-target-v5-0-10c8e078befb@linaro.org> In-Reply-To: <20240226-b4-qcom-common-target-v5-0-10c8e078befb@linaro.org> To: Neil Armstrong , Sumit Garg , Ramon Fried , Dzmitry Sankouski , Caleb Connolly , Peng Fan , Jaehoon Chung , Rayagonda Kokatanur , Lukasz Majewski , Sean Anderson , Jorge Ramirez-Ortiz , Stephan Gerhold Cc: Marek Vasut , u-boot@lists.denx.de X-Mailer: b4 0.13-dev-4bd13 X-Developer-Signature: v=1; a=openpgp-sha256; l=3504; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=WbAiHiP+Ske4PP+2WCzE8n7QvlRlw7OUnKXu/sGU8CU=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhtQ7J3eylsf1rr66qqGKI/7g3vSLjcoWVqtWdmzadMz1r qXuhXceHaUsDIIcDLJiiiziJ5ZZNq29bK+xfcEFmDmsTCBDGLg4BWAi83IZ/hnJBU75Fm11480P azHld0zXA+8o6bIoeBm83v9yWVUD70FGhjnh8g37HzlNSdCWmL7kkpVAd6jl0z2Rvk9qfvqrPWq 5qgYA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Use the clk_* helper functions and the correct property name for clocks. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Tested-by: Sumit Garg #qcs404 Signed-off-by: Caleb Connolly --- drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index fe1e754bfde0..059cb3da77c5 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -43,8 +43,9 @@ struct msm_sdhc_plat { struct msm_sdhc { struct sdhci_host host; void *base; + struct clk_bulk clks; }; struct msm_sdhc_variant_info { bool mci_removed; @@ -53,37 +54,59 @@ struct msm_sdhc_variant_info { DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) { - int node = dev_of_offset(dev); - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency", - 400000); - uint clkd[2]; /* clk_id and clk_no */ - int clk_offset; - struct udevice *clk_dev; - struct clk clk; - int ret; + struct msm_sdhc *prv = dev_get_priv(dev); + ofnode node = dev_ofnode(dev); + ulong clk_rate; + int ret, i = 0, n_clks; + const char *clk_name; - ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2); + ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate)); if (ret) - return ret; + clk_rate = 400000; - clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]); - if (clk_offset < 0) - return clk_offset; - - ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev); - if (ret) + ret = clk_get_bulk(dev, &prv->clks); + if (ret) { + log_warning("Couldn't get mmc clocks: %d\n", ret); return ret; + } - clk.id = clkd[1]; - ret = clk_request(clk_dev, &clk); - if (ret < 0) + ret = clk_enable_bulk(&prv->clks); + if (ret) { + log_warning("Couldn't enable mmc clocks: %d\n", ret); return ret; + } - ret = clk_set_rate(&clk, clk_rate); - if (ret < 0) - return ret; + /* If clock-names is unspecified, then the first clock is the core clock */ + if (!ofnode_get_property(node, "clock-names", &n_clks)) { + if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) { + log_warning("Couldn't set core clock rate: %d\n", ret); + return -EINVAL; + } + } + + /* Find the index of the "core" clock */ + while (i < n_clks) { + ofnode_read_string_index(node, "clock-names", i, &clk_name); + if (!strcmp(clk_name, "core")) + break; + i++; + } + + if (i >= prv->clks.count) { + log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i, + prv->clks.count); + return -EINVAL; + } + + /* The clock is already enabled by the clk_bulk above */ + clk_rate = clk_set_rate(&prv->clks.clks[i], clk_rate); + /* If we get a rate of 0 then something has probably gone wrong. */ + if (clk_rate == 0 || IS_ERR((void *)clk_rate)) { + log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate ? (int)PTR_ERR((void *)clk_rate) : 0); + return -EINVAL; + } return 0; } @@ -186,8 +209,10 @@ static int msm_sdc_remove(struct udevice *dev) /* Disable host-controller mode */ if (!var_info->mci_removed) writel(0, priv->base + SDCC_MCI_HC_MODE); + clk_release_bulk(&priv->clks); + return 0; } static int msm_of_to_plat(struct udevice *dev)