diff mbox series

[v1,07/17] doc: device-tree-bindings: misc: add secreg text file for agilex5

Message ID 20230621031610.28401-8-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series Agilex5 Platform Enablement | expand

Commit Message

Jit Loon Lim June 21, 2023, 3:16 a.m. UTC 
This is for new platform enablement for agilex5.
Add new secure register text file for new platform.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 .../misc/socfpga_secreg.txt                   | 397 ++++++++++++++++++
 1 file changed, 397 insertions(+)
 create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt
diff mbox series

Patch

diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt
new file mode 100644
index 0000000000..97640b74d9
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt
@@ -0,0 +1,397 @@ 
+* Firewall and privilege register settings in device tree
+
+Required properties:
+--------------------
+
+- compatible: should contain "intel,socfpga-secreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+			 followed by 32-bit value settings and
+			 the masking bits, only masking bit
+			 set to 1 allows modification.
+
+The device tree node which describes secure and privilege register access
+configuration in compile time.
+
+Most of these registers are expected to work except for the case which some
+registers configuration are required for granting access to some other
+registers, for example CCU registers have to be properly configured before
+allowing register configuration access to fpga2sdram firewall as shown in
+below example.
+
+Some registers depend on runtime data for proper configuration are expected
+to be part of driver that generating these data for example configuration for
+soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from
+memory device tree node.
+
+Please refer details of tested examples below for both fpga2sdram and QoS
+configuration with default reset value and the comments.
+
+Example:
+--------
+
+Common configuration for all SoC64 devices:
+Path: arch/arm/dts/socfpga_soc64_u-boot.dtsi
+
+	socfpga_secreg: socfpga-secreg {
+		compatible = "intel,socfpga-secreg";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		i_sys_mgr_core@ffd12000 {
+			reg = <0xffd12000 0x00000230>;
+			intel,offset-settings =
+				/* Enable non-secure interface to DMA */
+				<0x00000020 0xff010000 0xff010011>,
+				/* Enable non-secure interface to DMA periph */
+				<0x00000024 0xffffffff 0xffffffff>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_l4_per_l4_per_scr@ffd21000 {
+			reg = <0xffd21000 0x00000074>;
+			intel,offset-settings =
+				/* Disable L4 periphs firewall */
+				<0x00000000 0x01010001 0x01010001>,
+				<0x00000004 0x01010001 0x01010001>,
+				<0x0000000c 0x01010001 0x01010001>,
+				<0x00000010 0x01010001 0x01010001>,
+				<0x0000001c 0x01010001 0x01010101>,
+				<0x00000020 0x01010001 0x01010101>,
+				<0x00000024 0x01010001 0x01010101>,
+				<0x00000028 0x01010001 0x01010101>,
+				<0x0000002c 0x01010001 0x01010001>,
+				<0x00000030 0x01010001 0x01010001>,
+				<0x00000034 0x01010001 0x01010001>,
+				<0x00000040 0x01010001 0x01010001>,
+				<0x00000044 0x01010001 0x01010101>,
+				<0x00000048 0x01010001 0x01010101>,
+				<0x00000050 0x01010001 0x01010101>,
+				<0x00000054 0x01010001 0x01010101>,
+				<0x00000058 0x01010001 0x01010101>,
+				<0x0000005c 0x01010001 0x01010101>,
+				<0x00000060 0x01010001 0x01010101>,
+				<0x00000064 0x01010001 0x01010101>,
+				<0x00000068 0x01010001 0x01010101>,
+				<0x0000006c 0x01010001 0x01010101>,
+				<0x00000070 0x01010001 0x01010101>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_l4_sys_l4_sys_scr@ffd21100 {
+			reg = <0xffd21100 0x00000098>;
+			intel,offset-settings =
+				/* Disable L4 system firewall */
+				<0x00000008 0x01010001 0x01010001>,
+				<0x0000000c 0x01010001 0x01010001>,
+				<0x00000010 0x01010001 0x01010001>,
+				<0x00000014 0x01010001 0x01010001>,
+				<0x00000018 0x01010001 0x01010001>,
+				<0x0000001c 0x01010001 0x01010001>,
+				<0x00000020 0x01010001 0x01010001>,
+				<0x0000002c 0x01010001 0x01010001>,
+				<0x00000030 0x01010001 0x01010001>,
+				<0x00000034 0x01010001 0x01010001>,
+				<0x00000038 0x01010001 0x01010001>,
+				<0x00000040 0x01010001 0x01010001>,
+				<0x00000044 0x01010001 0x01010001>,
+				<0x00000048 0x01010001 0x01010001>,
+				<0x0000004c 0x01010001 0x01010001>,
+				<0x00000054 0x01010001 0x01010001>,
+				<0x00000058 0x01010001 0x01010001>,
+				<0x0000005c 0x01010001 0x01010001>,
+				<0x00000060 0x01010001 0x01010101>,
+				<0x00000064 0x01010001 0x01010101>,
+				<0x00000068 0x01010001 0x01010101>,
+				<0x0000006c 0x01010001 0x01010101>,
+				<0x00000070 0x01010001 0x01010101>,
+				<0x00000074 0x01010001 0x01010101>,
+				<0x00000078 0x01010001 0x03010001>,
+				<0x00000090 0x01010001 0x01010001>,
+				<0x00000094 0x01010001 0x01010001>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_soc2fpga_soc2fpga_scr@ffd21200 {
+			reg = <0xffd21200 0x00000004>;
+			/* Disable soc2fpga security access */
+			intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 {
+			reg = <0xffd21300 0x00000004>;
+			/* Disable lightweight soc2fpga security access */
+			intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_tcu_tcu_scr@ffd21400 {
+			reg = <0xffd21400 0x00000004>;
+			/* Disable DMA ECC security access, for SMMU use */
+			intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
+			u-boot,dm-pre-reloc;
+		};
+
+		noc_fw_priv_MemoryMap_priv@ffd24800 {
+			reg = <0xffd24800 0x0000000c>;
+			intel,offset-settings =
+				/* Enable non-prviledged access to various periphs */
+				<0x00000000 0xfff73ffb 0xfff73ffb>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+configuration for N5X device:
+Path: arch/arm/dts/socfpga_n5x-u-boot.dtsi
+
+	&socfpga_secreg {
+		coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+			reg = <0xf7100200 0x00000014>;
+			intel,offset-settings =
+				/* Disable ocram security at CCU for non secure access */
+				<0x0000004 0x8000ffff 0xe007ffff>,
+				<0x0000008 0x8000ffff 0xe007ffff>,
+				<0x000000c 0x8000ffff 0xe007ffff>,
+				<0x0000010 0x8000ffff 0xe007ffff>;
+			u-boot,dm-pre-reloc;
+		};
+
+		soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+			reg = <0xf8020000 0x0000001c>;
+			intel,offset-settings =
+				/* Disable MPFE firewall for SMMU */
+				<0x00000000 0x00010101 0x00010101>,
+				/* Disable MPFE firewall for HMC adapter */
+				<0x00000004 0x00000001 0x00010101>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+configuration for Agilex device:
+Path: arch/arm/dts/socfpga_agilex-u-boot.dtsi
+
+	&socfpga_secreg {
+		CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+			reg = <0xf7100200 0x00000014>;
+			intel,offset-settings =
+				/* Disable ocram security at CCU for non secure access */
+				<0x0000004 0x8000ffff 0xe003ffff>,
+				<0x0000008 0x8000ffff 0xe003ffff>,
+				<0x000000c 0x8000ffff 0xe003ffff>,
+				<0x0000010 0x8000ffff 0xe003ffff>;
+			u-boot,dm-pre-reloc;
+		};
+
+		soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+			reg = <0xf8020000 0x0000001c>;
+			intel,offset-settings =
+				/* Disable MPFE firewall for SMMU */
+				<0x00000000 0x00010101 0x00010101>,
+				/* Disable MPFE firewall for HMC adapter */
+				<0x00000004 0x00000001 0x00010101>;
+			u-boot,dm-pre-reloc;
+		};
+
+		/*
+		 * Below are all fpga2sdram firewall settings with default
+		 * reset value for the sake of easy reference by users.
+		 * Users may choose to remove any of these register
+		 * configurations that they do not require in their specific
+		 * implementation.
+		 */
+		soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 {
+			reg = <0xf8020100 0x00000050>;
+			intel,offset-settings =
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x000000ff>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x000000ff>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x000000ff>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x000000ff>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x000000ff>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x000000ff>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x000000ff>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x000000ff>;
+			u-boot,dm-pre-reloc;
+		};
+
+		/*
+		 * Example of ccu_mem0_I_main QOS settings with
+		 * default reset value for the sake of easy reference
+		 * by users. Users may choose to remove any of these register
+		 * configurations that they do not require in their specific
+		 * implementation.
+		 */
+		soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
+			reg = <0xf8022080 0x0000001c>;
+			intel,offset-settings =
+				<0x0000008 0x00000200 0x00000303>,
+				<0x000000c 0x00000003 0x00000003>,
+				<0x0000010 0x00000BFE 0x00007fff>,
+				<0x0000014 0x00000008 0x000003ff>,
+				<0x0000018 0x00000000 0x0000000f>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+configuration for Stratix 10 device:
+Path: arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+
+	&socfpga_secreg {
+		i_ccu_noc_registers@f7000000 {
+			reg = <0xf7000000 0x00049e60>;
+			intel,offset-settings =
+				/* Enable access to DDR reg from CPU */
+				<0x0004400 0xF8000000 0xffffffff>,
+
+				/* Enable access to DDR region from CPU */
+				<0x00045c0 0x00000000 0xffffffdf>,
+				<0x00045e0 0x00000000 0xffffffdf>,
+				<0x0004600 0x00000000 0xffffffdf>,
+				<0x0004620 0x00000000 0xffffffdf>,
+				<0x0004640 0x00000000 0xffffffdf>,
+				<0x0004660 0x00000000 0xffffffdf>,
+
+				/* Disable ocram security at CCU for non secure access */
+				<0x0004688 0xfffc0000 0xffffffcf>,
+				<0x0018628 0xfffc0000 0xffffffcf>,
+
+				/* Enable access to DDR region from IO master */
+				<0x00018560 0x00000000 0xffffffdf>,
+				<0x00018580 0x00000000 0xffffffdf>,
+				<0x000185a0 0x00000000 0xffffffdf>,
+				<0x000185c0 0x00000000 0xffffffdf>,
+				<0x000185e0 0x00000000 0xffffffdf>,
+				<0x00018600 0x00000000 0xffffffdf>,
+
+				/* Enable access to DDR region from TCU */
+				<0x0002c520 0x00000000 0xffffffdf>,
+				<0x0002c540 0x00000000 0xffffffdf>,
+				<0x0002c560 0x00000000 0xffffffdf>,
+				<0x0002c580 0x00000000 0xffffffdf>,
+				<0x0002c5a0 0x00000000 0xffffffdf>,
+				<0x0002c5c0 0x00000000 0xffffffdf>,
+
+				/* Enable access to DDR region from FPGA */
+				<0x000105a0 0x00000000 0xffffffdf>,
+				<0x000105c0 0x00000000 0xffffffdf>,
+				<0x000105e0 0x00000000 0xffffffdf>,
+				<0x00010600 0x00000000 0xffffffdf>,
+				<0x00010620 0x00000000 0xffffffdf>,
+				<0x00010640 0x00000000 0xffffffdf>;
+			u-boot,dm-pre-reloc;
+		};
+
+		/*
+		 * Both firewall and QOS regs accessed by CPU in MPFE has
+		 * dependency on CCU configuration above.
+		 *
+		 * Below are all fpga2sdram firewall settings with default
+		 * reset value for the sake of easy reference by users.
+		 * Users may choose to remove any of these register configurations
+		 * that they do not require in their specific implementation.
+		 */
+		soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020200 {
+			reg = <0xf8020200 0x00000050>;
+			intel,offset-settings =
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
+			u-boot,dm-pre-reloc;
+		};
+
+		soc_noc_fw_ddr_fpga2sdram_inst_1_ddr_scr@f8020300 {
+			reg = <0xf8020300 0x00000050>;
+			intel,offset-settings =
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
+			u-boot,dm-pre-reloc;
+		};
+
+		soc_noc_fw_ddr_fpga2sdram_inst_2_ddr_scr@f8020400 {
+			reg = <0xf8020400 0x00000050>;
+			intel,offset-settings =
+				<0x0000000 0x00000000 0x0000000f>,
+				<0x0000004 0x00000000 0x0000000f>,
+				<0x0000008 0x00000000 0x0000000f>,
+				<0x0000010 0x00000000 0xffff0000>,
+				<0x0000014 0x00000000 0x0000001f>,
+				<0x0000018 0x00000000 0xffff0000>,
+				<0x000001c 0x00000000 0x0000001f>,
+				<0x0000020 0x00000000 0xffff0000>,
+				<0x0000024 0x00000000 0x0000001f>,
+				<0x0000028 0x00000000 0xffff0000>,
+				<0x000002c 0x00000000 0x0000001f>,
+				<0x0000030 0x00000000 0xffff0000>,
+				<0x0000034 0x00000000 0x0000001f>,
+				<0x0000038 0x00000000 0xffff0000>,
+				<0x000003c 0x00000000 0x0000001f>,
+				<0x0000040 0x00000000 0xffff0000>,
+				<0x0000044 0x00000000 0x0000001f>,
+				<0x0000048 0x00000000 0xffff0000>,
+				<0x000004c 0x00000000 0x0000001f>;
+			u-boot,dm-pre-reloc;
+		};
+
+		/*
+		 * Example of ccu_mem0_I_main QOS settings with
+		 * default reset value for the sake of easy reference
+		 * by users. Users may choose to remove any of these register
+		 * configurations that they do not require in their specific
+		 * implementation.
+		 */
+		soc_ddr_scheduler_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 {
+			reg = <0xf8022080 0x0000001c>;
+			intel,offset-settings =
+				<0x0000008 0x00000000 0x00000303>,
+				<0x000000c 0x00000001 0x00000003>,
+				<0x0000010 0x00000BFE 0x00001fff>,
+				<0x0000014 0x00000008 0x000003ff>,
+				<0x0000018 0x00000000 0x00000007>;
+			u-boot,dm-pre-reloc;
+		};
+	};