| Message ID | 20230621031610.28401-2-jit.loon.lim@intel.com |
|---|---|
| State | Needs Review / ACK, archived |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Agilex5 Platform Enablement | expand |
Hi Jit Loon, > -----Original Message----- > From: Lim, Jit Loon <jit.loon.lim@intel.com> > Sent: Wednesday, 21 June, 2023 11:16 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki <jagan@amarulasolutions.com>; Vignesh R > <vigneshr@ti.com>; Vasut, Marek <marex@denx.de>; Simon > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Hea, Kok Kiang <kok.kiang.hea@intel.com>; > Lokanathan, Raaj <raaj.lokanathan@intel.com>; Maniyam, Dinesh > <dinesh.maniyam@intel.com>; Ng, Boon Khai <boon.khai.ng@intel.com>; > Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>; Chong, Teik Heng > <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat > <muhammad.hazim.izzat.zamri@intel.com>; Lim, Jit Loon > <jit.loon.lim@intel.com>; Tang, Sieu Mun <sieu.mun.tang@intel.com> > Subject: [PATCH v1 01/17] arch: arm: update kconfig for new platform agilex5 > > This is for new platform enablement for agilex5 > > Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> > --- > arch/arm/Kconfig | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > 99264a6478..8e36456fa8 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA > select SPL_LIBGENERIC_SUPPORT > select SPL_OF_CONTROL > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 > + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 > + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 Please exclude these changes for now because this driver is not in mainline yet. You can submit another patch for these changes once the driver is accepted into mainline. > select SPL_SERIAL > select SPL_SYSRESET > select SPL_WATCHDOG > @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select SYSRESET > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 > && TARGET_SOCFPGA_SOC64 > + imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 Please update your commit message, your message should be clear and accurate to reflect your changes here. > imply CMD_DM > imply CMD_MTDPARTS > imply CRC32_VERIFY > -- > 2.26.2 Thanks and regards, Tien Fong
> -----Original Message----- > From: Chee, Tien Fong <tien.fong.chee@intel.com> > Sent: Wednesday, 28 June, 2023 4:17 PM > To: Lim, Jit Loon <jit.loon.lim@intel.com>; u-boot@lists.denx.de > Cc: Jagan Teki <jagan@amarulasolutions.com>; Vignesh R > <vigneshr@ti.com>; Vasut, Marek <marex@denx.de>; Simon > <simon.k.r.goldschmidt@gmail.com>; Hea, Kok Kiang > <kok.kiang.hea@intel.com>; Lokanathan, Raaj <raaj.lokanathan@intel.com>; > Maniyam, Dinesh <dinesh.maniyam@intel.com>; Ng, Boon Khai > <boon.khai.ng@intel.com>; Yuslaimi, Alif Zakuan > <alif.zakuan.yuslaimi@intel.com>; Chong, Teik Heng > <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat > <muhammad.hazim.izzat.zamri@intel.com>; Tang, Sieu Mun > <sieu.mun.tang@intel.com> > Subject: RE: [PATCH v1 01/17] arch: arm: update kconfig for new platform > agilex5 > > Hi Jit Loon, > > > -----Original Message----- > > From: Lim, Jit Loon <jit.loon.lim@intel.com> > > Sent: Wednesday, 21 June, 2023 11:16 AM > > To: u-boot@lists.denx.de > > Cc: Jagan Teki <jagan@amarulasolutions.com>; Vignesh R > > <vigneshr@ti.com>; Vasut, Marek <marex@denx.de>; Simon > > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > > <tien.fong.chee@intel.com>; Hea, Kok Kiang <kok.kiang.hea@intel.com>; > > Lokanathan, Raaj <raaj.lokanathan@intel.com>; Maniyam, Dinesh > > <dinesh.maniyam@intel.com>; Ng, Boon Khai <boon.khai.ng@intel.com>; > > Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>; Chong, Teik > > Heng <teik.heng.chong@intel.com>; Zamri, Muhammad Hazim Izzat > > <muhammad.hazim.izzat.zamri@intel.com>; Lim, Jit Loon > > <jit.loon.lim@intel.com>; Tang, Sieu Mun <sieu.mun.tang@intel.com> > > Subject: [PATCH v1 01/17] arch: arm: update kconfig for new platform > > agilex5 > > > > This is for new platform enablement for agilex5 > > > > Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> > > --- > > arch/arm/Kconfig | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 99264a6478..8e36456fa8 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA > > select SPL_LIBGENERIC_SUPPORT > > select SPL_OF_CONTROL > > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 > > + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 > > + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 > > Please exclude these changes for now because this driver is not in mainline > yet. You can submit another patch for these changes once the driver is > accepted into mainline. > > > select SPL_SERIAL > > select SPL_SYSRESET > > select SPL_WATCHDOG > > @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA > > select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || > > TARGET_SOCFPGA_ARRIA10 > > select SYSRESET > > select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || > > TARGET_SOCFPGA_ARRIA10 > > - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 > > + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 > > && TARGET_SOCFPGA_SOC64 > > + imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 > > Please update your commit message, your message should be clear and > accurate to reflect your changes here. > > > imply CMD_DM > > imply CMD_MTDPARTS > > imply CRC32_VERIFY > > -- > > 2.26.2 > > Thanks and regards, > Tien Fong Ok. Will update commit message and send out in v2 for review.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 99264a6478..8e36456fa8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1093,6 +1093,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG @@ -1101,7 +1103,8 @@ config ARCH_SOCFPGA select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && TARGET_SOCFPGA_SOC64 + imply SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY
This is for new platform enablement for agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> --- arch/arm/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)