Message ID | 20230306145354.7439-6-marex@denx.de |
---|---|
State | Accepted |
Commit | a79de0808a8dc738ec2076ad47d431c64452111e |
Delegated to: | Stefano Babic |
Headers | show |
Series | [v4,01/14] clk: imx8mp: Add EQoS MAC clock | expand |
> The driver currently only waits for DMA_MODE SWR bit to clear itself. > This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset > before IOMUX GPR[1] content is latched into the MAC and used. Without > the proper reset, the i.MX8M Plus MAC variant does not take the value > in IOMUX GPR[1] into account, which makes it impossible e.g. to switch > interface mode from RGMII to any other. > Since proper reset is desired in general to put the block into defined > state, always assert the DMA_MODE SWR bit before waiting for the bit > to clear itself. > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> > Signed-off-by: Marek Vasut <marex@denx.de> Applied to u-boot-imx, next, thanks ! Best regards, Stefano Babic
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9a5575e7b83..ec58697b311 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev) eqos->reg_access_ok = true; + /* + * Assert the SWR first, the actually reset the MAC and to latch in + * e.g. i.MX8M Plus GPR[1] content, which selects interface mode. + */ + setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); + ret = wait_for_bit_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR, false, eqos->config->swr_wait, false);