@@ -1645,6 +1645,7 @@ config TARGET_LS1021AQDS
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
+ select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
@@ -1663,6 +1664,7 @@ config TARGET_LS1021ATWR
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
+ select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
@@ -1727,6 +1729,7 @@ config TARGET_LS1021AIOT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select PEN_ADDR_BIG_ENDIAN
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select GPIO_EXTRA_HEADER
@@ -51,6 +51,9 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config PEN_ADDR_BIG_ENDIAN
+ bool
+
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
@@ -68,7 +68,6 @@
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
@@ -242,7 +242,6 @@
* MMC
*/
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
@@ -152,7 +152,6 @@
/* GPIO */
-#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define HWCONFIG_BUFFER_SIZE 256
This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++ include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 5 files changed, 6 insertions(+), 3 deletions(-)