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[2603:6081:7b00:6400:f99b:6f1a:2cc1:7368]) by smtp.gmail.com with ESMTPSA id b23-20020a1709062b5700b007c0991735c0sm3434248ejg.79.2022.12.02.13.43.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 13:43:26 -0800 (PST) From: Tom Rini To: u-boot@lists.denx.de Subject: [PATCH 30/41] Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig Date: Fri, 2 Dec 2022 16:42:40 -0500 Message-Id: <20221202214251.3027264-30-trini@konsulko.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221202214251.3027264-1-trini@konsulko.com> References: <20221127152536.1556469-41-trini@konsulko.com> <20221202214251.3027264-1-trini@konsulko.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini --- arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++ include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 5 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb382ea1d70..42576e503a4a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1645,6 +1645,7 @@ config TARGET_LS1021AQDS select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select SYS_FSL_DDR select FSL_DDR_INTERACTIVE @@ -1663,6 +1664,7 @@ config TARGET_LS1021ATWR select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1727,6 +1729,7 @@ config TARGET_LS1021AIOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 7e138e0cc5be..a83eb7e8fdd1 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -51,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 179c5128e3b1..0e3ff3c5b7a4 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,6 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fead9edeccdc..76e75335c588 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,6 @@ * MMC */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b07978a999e2..281b26fa2ba0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -152,7 +152,6 @@ /* GPIO */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256