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[2/2] arm: socfpga: soc64: Perform warm reset after L2 reset in SPL on S10

Message ID 20220831112044.25371-3-jit.loon.lim@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series *** SUBJECT HERE *** | expand

Commit Message

Jit Loon Lim Aug. 31, 2022, 11:20 a.m. UTC 
From: Chee Hong Ang <chee.hong.ang@intel.com>

SPL checks for magic word in system manager's scratch register
to find out whether the system has performed L2 reset. If L2
reset was performed, SPL put all slave CPUs (CPU1-3) into WFI
mode. Master CPU (CPU0) requests warm reset via RMR_EL3 system
register and put itself into WFI mode. Firmware will get the
warm reset request from HPS and perform the warm reset sequence
to reboot all the HPS cores.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 arch/arm/mach-socfpga/lowlevel_init_soc64.S | 24 +++++++++++++++++++++
 1 file changed, 24 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
index 875927cc4d..1fd0a50b3a 100644
--- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S
+++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S
@@ -12,6 +12,30 @@ 
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+#ifdef CONFIG_SPL_BUILD
+	/* Check for L2 reset magic word */
+	ldr	x4, =L2_RESET_DONE_REG
+	ldr	x5, [x4]
+	ldr	x1, =L2_RESET_DONE_STATUS
+	cmp	x1, x5
+	/* No L2 reset, skip warm reset */
+	b.ne	skipwarmreset
+	/* L2 reset completed */
+	str	xzr, [x4]
+	/* Put all slaves CPUs into WFI mode */
+	branch_if_slave x0, put_cpu_in_wfi
+	/* Master CPU (CPU0) request for warm reset */
+	mrs	x1, rmr_el3
+	orr	x1, x1, #0x02
+	msr	rmr_el3, x1
+	isb
+	dsb	sy
+put_cpu_in_wfi:
+	wfi
+	b	put_cpu_in_wfi
+skipwarmreset:
+#endif
+
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
 wait_for_atf: