@@ -10,6 +10,7 @@ void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void print_reset_info(void);
void socfpga_bridges_reset(int enable);
+void l2_reset_cpu(void);
#define RSTMGR_SOC64_STATUS 0x00
#define RSTMGR_SOC64_MPUMODRST 0x20
@@ -5,19 +5,73 @@
*/
#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/secure.h>
static int socfpga_sysreset_request(struct udevice *dev,
enum sysreset_t type)
{
- puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
- mbox_reset_cold();
+#ifndef CONFIG_SPL_BUILD
+ const char *reset = env_get("reset");
+
+ if (reset && !strcmp(reset, "warm")) {
+ /* flush dcache */
+ flush_dcache_all();
+
+ /* request a warm reset */
+ puts("Do warm reset now...\n");
+ l2_reset_cpu();
+ } else {
+#endif
+ puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n");
+ mbox_reset_cold();
+#ifndef CONFIG_SPL_BUILD
+ }
+#endif
+
return -EINPROGRESS;
}
+void l2_reset_cpu(void)
+{
+ asm volatile(
+ "str %0, [%1]\n"
+ /* Increase timeout in rstmgr.hdsktimeout */
+ "ldr x2, =0xFFFFFF\n"
+ "str w2, [%2, #0x64]\n"
+ "ldr w2, [%2, #0x10]\n"
+ /*
+ * Set l2flushen = 1, etrstallen = 1,
+ * fpgahsen = 1 and sdrselfrefen = 1
+ * in rstmgr.hdsken to perform handshake
+ * in certain peripherals before trigger
+ * L2 reset.
+ */
+ "ldr x3, =0x10D\n"
+ "orr x2, x2, x3\n"
+ "str w2, [%2, #0x10]\n"
+ /* Trigger L2 reset in rstmgr.coldmodrst */
+ "ldr w2, [%2, #0x34]\n"
+ "orr x2, x2, #0x100\n"
+ "isb\n"
+ "dsb sy\n"
+ "str w2, [%2, #0x34]\n"
+ /* Put all cores into WFI mode */
+ "wfi_loop:\n"
+ " wfi\n"
+ " b wfi_loop\n"
+ : : "r" (L2_RESET_DONE_STATUS),
+ "r" (L2_RESET_DONE_REG),
+ "r" (SOCFPGA_RSTMGR_ADDRESS)
+ : "x1", "x2", "x3");
+}
+
static struct sysreset_ops socfpga_sysreset = {
.request = socfpga_sysreset_request,
};
@@ -16,6 +16,13 @@
*/
/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
#define CPU_RELEASE_ADDR 0xFFD12210
+/*
+ * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR
+ * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3.
+ */
+#define L2_RESET_DONE_REG 0xFFD12218
+/* Magic word to indicate L2 reset is completed */
+#define L2_RESET_DONE_STATUS 0x1228E5E7
/*
* U-Boot console configurations