diff mbox series

[v7,5/6] rockchip: px30: add support for SFC for Odroid Go Advance

Message ID 20210805162301.v7.5.Id7d2651c4d3564a1c72eeef29a01f6575259009d@changeid
State Accepted
Commit d70c0cab8f8bb8607f574e0e346d14cea1729903
Delegated to: Kever Yang
Headers show
Series rockchip_sfc: add support for Rockchip SFC | expand

Commit Message

Jon Lin Aug. 5, 2021, 8:27 a.m. UTC
From: Chris Morgan <macromorgan@hotmail.com>

The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
and rx lines to 2 for this reason.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---

(no changes since v1)

 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
 arch/arm/dts/rk3326-odroid-go2.dts         | 16 ++++++++++++++++
 2 files changed, 33 insertions(+)

Comments

Chris Morgan Aug. 5, 2021, 5:32 p.m. UTC | #1
On Thu, Aug 05, 2021 at 04:27:52PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
> XT25F128B SPI NOR flash chip. This adds support for both. Note that
> while both the controller and chip support quad mode, only two lines
> are connected to the chip. Changing the pinctrl to bus2 and setting tx
> and rx lines to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> (no changes since v1)
> 
>  arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
>  arch/arm/dts/rk3326-odroid-go2.dts         | 16 ++++++++++++++++
>  2 files changed, 33 insertions(+)
> 
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 00767d2abd..741e8dd935 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -7,6 +7,15 @@
>  	chosen {
>  		u-boot,spl-boot-order = &sdmmc;
>  	};
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		mmc0 = &sdmmc;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		spi0 = &sfc;
> +	};
>  };
>  
>  &cru {
> @@ -57,6 +66,14 @@
>  	u-boot,spl-fifo-mode;
>  };
>  
> +&sfc {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&spi_flash {
> +	u-boot,dm-pre-reloc;
> +};

See comments below. If we change that devicetree node to match upstream
linux proposed patch, we'll need to change this to the following:

&{/sfc@ff3a0000/flash@0} {
	u-boot,dm-pre-reloc;
};

> +
>  &uart1 {
>  	clock-frequency = <24000000>;
>  	u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 8cd4688c49..6f91f5040b 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -617,6 +617,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
> +	status = "okay";
> +
> +	spi_flash: xt25f128b@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;
> +	};

Let's add support for this exactly how we have it queued up for the
mainline kernel. I've tested the following devicetree configuration
and it works for me. For anyone else reading, note that in Linux
the chip fails if the spi-tx-bus-width is set to 2 but not 1,
there seems to be something implementation specific for the OGA
that requires this setting. U-Boot is not affected, however,
but setting it here anyway to match upstream Linux is wise. Jon
could not reproduce the issue on his px30 based hardware, but
I could always reproduce the issue on my Odroid Go Advance.

&sfc {
	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
	pinctrl-names = "default";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <108000000>;
		spi-rx-bus-width = <2>;
		spi-tx-bus-width = <1>;
	};
};

> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
>
Kever Yang Aug. 11, 2021, 10:20 a.m. UTC | #2
On 2021/8/5 下午4:27, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
> XT25F128B SPI NOR flash chip. This adds support for both. Note that
> while both the controller and chip support quad mode, only two lines
> are connected to the chip. Changing the pinctrl to bus2 and setting tx
> and rx lines to 2 for this reason.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>
> (no changes since v1)
>
>   arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
>   arch/arm/dts/rk3326-odroid-go2.dts         | 16 ++++++++++++++++
>   2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 00767d2abd..741e8dd935 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -7,6 +7,15 @@
>   	chosen {
>   		u-boot,spl-boot-order = &sdmmc;
>   	};
> +
> +	aliases {
> +		i2c0 = &i2c0;
> +		i2c1 = &i2c1;
> +		mmc0 = &sdmmc;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		spi0 = &sfc;
> +	};
>   };
>   
>   &cru {
> @@ -57,6 +66,14 @@
>   	u-boot,spl-fifo-mode;
>   };
>   
> +&sfc {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&spi_flash {
> +	u-boot,dm-pre-reloc;
> +};
> +
>   &uart1 {
>   	clock-frequency = <24000000>;
>   	u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 8cd4688c49..6f91f5040b 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -617,6 +617,22 @@
>   	status = "okay";
>   };
>   
> +&sfc {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
> +	status = "okay";
> +
> +	spi_flash: xt25f128b@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;
> +	};
> +};
> +
>   &tsadc {
>   	status = "okay";
>   };
diff mbox series

Patch

diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..741e8dd935 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -7,6 +7,15 @@ 
 	chosen {
 		u-boot,spl-boot-order = &sdmmc;
 	};
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdmmc;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		spi0 = &sfc;
+	};
 };
 
 &cru {
@@ -57,6 +66,14 @@ 
 	u-boot,spl-fifo-mode;
 };
 
+&sfc {
+	u-boot,dm-pre-reloc;
+};
+
+&spi_flash {
+	u-boot,dm-pre-reloc;
+};
+
 &uart1 {
 	clock-frequency = <24000000>;
 	u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 8cd4688c49..6f91f5040b 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -617,6 +617,22 @@ 
 	status = "okay";
 };
 
+&sfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
+	status = "okay";
+
+	spi_flash: xt25f128b@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <108000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+	};
+};
+
 &tsadc {
 	status = "okay";
 };