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[v1,1/2] x86: sipi_vector: Append appropriate suffixes

Message ID 20200728095626.28445-1-andriy.shevchenko@linux.intel.com
State Accepted
Commit 549c6f47e67546e1fee87c0bae2ab84af9a9a693
Delegated to: Bin Meng
Headers show
Series [v1,1/2] x86: sipi_vector: Append appropriate suffixes | expand

Commit Message

Andy Shevchenko July 28, 2020, 9:56 a.m. UTC
Assembler is not happy:

arch/x86/cpu/sipi_vector.S: Assembler messages:
arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'
arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'

Fix this by adding appropriate suffixes to the assembler commands.

Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/cpu/sipi_vector.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Bin Meng Aug. 1, 2020, 12:26 a.m. UTC | #1
On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> Assembler is not happy:
>
> arch/x86/cpu/sipi_vector.S: Assembler messages:
> arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
> arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'
> arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
>
> Fix this by adding appropriate suffixes to the assembler commands.
>
> Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  arch/x86/cpu/sipi_vector.S | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng Aug. 3, 2020, 2:45 a.m. UTC | #2
On Sat, Aug 1, 2020 at 8:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Jul 28, 2020 at 5:56 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> >
> > Assembler is not happy:
> >
> > arch/x86/cpu/sipi_vector.S: Assembler messages:
> > arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
> > arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'
> > arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
> >
> > Fix this by adding appropriate suffixes to the assembler commands.
> >
> > Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> >  arch/x86/cpu/sipi_vector.S | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!
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Patch

diff --git a/arch/x86/cpu/sipi_vector.S b/arch/x86/cpu/sipi_vector.S
index 40cc27f1e1d0..fa1e6cb19af4 100644
--- a/arch/x86/cpu/sipi_vector.S
+++ b/arch/x86/cpu/sipi_vector.S
@@ -131,12 +131,12 @@  ap_start:
 	jnz	microcode_done
 
 	/* Determine if parallel microcode loading is allowed */
-	cmp	$0xffffffff, microcode_lock
+	cmpl	$0xffffffff, microcode_lock
 	je	load_microcode
 
 	/* Protect microcode loading */
 lock_microcode:
-	lock bts $0, microcode_lock
+	lock btsl $0, microcode_lock
 	jc	lock_microcode
 
 load_microcode:
@@ -154,7 +154,7 @@  load_microcode:
 	popa
 
 	/* Unconditionally unlock microcode loading */
-	cmp	$0xffffffff, microcode_lock
+	cmpl	$0xffffffff, microcode_lock
 	je	microcode_done
 
 	xor	%eax, %eax