diff mbox series

[PATCHv2,2/9] arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM config

Message ID 20200324081209.48449-3-Zhiqiang.Hou@nxp.com
State Changes Requested
Delegated to: Priyanka Jain
Headers show
Series fsl: layerscape: Initialize the GIC redistributor | expand

Commit Message

Z.Q. Hou March 24, 2020, 8:12 a.m. UTC 
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - No change.

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Priyanka Jain (OSS) April 15, 2020, 10:27 a.m. UTC | #1 
>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
>Sent: Tuesday, March 24, 2020 1:42 PM
>To: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>; Biwen Li
><biwen.li@nxp.com>
>Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
>Subject: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram if
>enabled RESV_RAM config
>
>From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
>The initialization of gd->arch.resv_ram pointer should depend on if the
>RESV_RAM config is enabled.
>
>Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>---
>V2:
> - No change.
>
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>index b443894453..1b7729c046 100644
>--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>@@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
> 	if (i > 0)
> 		ret = 0;
>
>-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
>+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> 	/* Assign memory for MC */
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> 	if (gd->bd->bi_dram[2].size >=
>@@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
> 				board_reserve_ram_top(gd->bd-
>>bi_dram[0].size);
> 		}
> 	}
>-#endif	/* CONFIG_FSL_MC_ENET */
>+#endif	/* CONFIG_RESV_RAM */
This memory block was intended to be used for MC. That's why earlier check was for "CONFIG_FSL_MC_ENET"
Are we planning to use this block for some other purpose as well?
Also I see "CONFIG_ RESV_RAM" getting defines later in the series.
Will MC will work if the series in applied partially?

Regards
Priyanka
> 	return ret;
> }
>@@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
> 	}
> #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
>
>-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
>+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> 	/* Assign memory for MC */
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> 	if (gd->bd->bi_dram[2].size >=
>@@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
> 				board_reserve_ram_top(gd->bd-
>>bi_dram[0].size);
> 		}
> 	}
>-#endif	/* CONFIG_FSL_MC_ENET */
>+#endif	/* CONFIG_RESV_RAM */
>
> #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
>--
>2.17.1
Z.Q. Hou April 15, 2020, 2:39 p.m. UTC | #2 
Hi Priyanka,

Thanks a lot for your comments!

> -----Original Message-----
> From: Priyanka Jain (OSS) <priyanka.jain@oss.nxp.com>
> Sent: 2020年4月15日 18:28
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; Biwen Li
> <biwen.li@nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: RE: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram if
> enabled RESV_RAM config
> 
> >-----Original Message-----
> >From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
> >Sent: Tuesday, March 24, 2020 1:42 PM
> >To: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>; Biwen
> >Li <biwen.li@nxp.com>
> >Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> >Subject: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram
> >if enabled RESV_RAM config
> >
> >From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> >The initialization of gd->arch.resv_ram pointer should depend on if the
> >RESV_RAM config is enabled.
> >
> >Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >---
> >V2:
> > - No change.
> >
> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >index b443894453..1b7729c046 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >@@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
> > 	if (i > 0)
> > 		ret = 0;
> >
> >-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> >+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> > 	/* Assign memory for MC */
> > #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> > 	if (gd->bd->bi_dram[2].size >=
> >@@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
> > 				board_reserve_ram_top(gd->bd-
> >>bi_dram[0].size);
> > 		}
> > 	}
> >-#endif	/* CONFIG_FSL_MC_ENET */
> >+#endif	/* CONFIG_RESV_RAM */
> This memory block was intended to be used for MC. That’s why earlier
> check was for "CONFIG_FSL_MC_ENET"
> Are we planning to use this block for some other purpose as well?
> Also I see "CONFIG_ RESV_RAM" getting defines later in the series.
> Will MC will work if the series in applied partially?

Yes, as you know this will be used for workaround of GICv3 redistributor tables
one-way reset issue.
The MC will not be affected, since FSL_MC_ENET selected RESV_RAM config.

Thanks,
Zhiqiang

> 
> Regards
> Priyanka
> > 	return ret;
> > }
> >@@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
> > 	}
> > #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
> >
> >-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> >+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> > 	/* Assign memory for MC */
> > #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> > 	if (gd->bd->bi_dram[2].size >=
> >@@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
> > 				board_reserve_ram_top(gd->bd-
> >>bi_dram[0].size);
> > 		}
> > 	}
> >-#endif	/* CONFIG_FSL_MC_ENET */
> >+#endif	/* CONFIG_RESV_RAM */
> >
> > #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
> > #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> >--
> >2.17.1
Wasim Khan April 21, 2020, 7:27 a.m. UTC | #3 
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
> Sent: Tuesday, March 24, 2020 1:42 PM
> To: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>; Biwen Li
> <biwen.li@nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram if
> enabled RESV_RAM config
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The initialization of gd->arch.resv_ram pointer should depend on if the
> RESV_RAM config is enabled.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - No change.
> 
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index b443894453..1b7729c046 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
>  	if (i > 0)
>  		ret = 0;
> 
> -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
>  	/* Assign memory for MC */
>  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
>  	if (gd->bd->bi_dram[2].size >=
> @@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
>  				board_reserve_ram_top(gd->bd-
> >bi_dram[0].size);
>  		}
>  	}
> -#endif	/* CONFIG_FSL_MC_ENET */
> +#endif	/* CONFIG_RESV_RAM */
> 
>  	return ret;
>  }
> @@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
>  	}
>  #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
> 
> -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
>  	/* Assign memory for MC */
>  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
>  	if (gd->bd->bi_dram[2].size >=
> @@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
>  				board_reserve_ram_top(gd->bd-
> >bi_dram[0].size);
>  		}
>  	}
> -#endif	/* CONFIG_FSL_MC_ENET */
> +#endif	/* CONFIG_RESV_RAM */
> 

CONFIG_FSL_MC_ENET will select the CONFIG_RESV_RAM. What benefit we have with this change ? 
because we are reserving memory for MC in the following code, so earlier check (with CONFIG_FSL_MC_ENET) looks good to be. 

>  #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
>  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> --
> 2.17.1
Z.Q. Hou April 25, 2020, 8:26 a.m. UTC | #4 
Hi Wasim,

Thanks a lot for your comments!

> -----Original Message-----
> From: Wasim Khan <wasim.khan@nxp.com>
> Sent: 2020年4月21日 15:27
> To: Z.q. Hou <zhiqiang.hou@nxp.com>; u-boot@lists.denx.de; Priyanka Jain
> <priyanka.jain@nxp.com>; Biwen Li <biwen.li@nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: RE: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram if
> enabled RESV_RAM config
> 
> 
> 
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Zhiqiang Hou
> > Sent: Tuesday, March 24, 2020 1:42 PM
> > To: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>; Biwen
> > Li <biwen.li@nxp.com>
> > Cc: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Subject: [PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram
> > if enabled RESV_RAM config
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The initialization of gd->arch.resv_ram pointer should depend on if
> > the RESV_RAM config is enabled.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V2:
> >  - No change.
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index b443894453..1b7729c046 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
> >  	if (i > 0)
> >  		ret = 0;
> >
> > -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> > +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> >  	/* Assign memory for MC */
> >  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> >  	if (gd->bd->bi_dram[2].size >=
> > @@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
> >  				board_reserve_ram_top(gd->bd-
> > >bi_dram[0].size);
> >  		}
> >  	}
> > -#endif	/* CONFIG_FSL_MC_ENET */
> > +#endif	/* CONFIG_RESV_RAM */
> >
> >  	return ret;
> >  }
> > @@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
> >  	}
> >  #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
> >
> > -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> > +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> >  	/* Assign memory for MC */
> >  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> >  	if (gd->bd->bi_dram[2].size >=
> > @@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
> >  				board_reserve_ram_top(gd->bd-
> > >bi_dram[0].size);
> >  		}
> >  	}
> > -#endif	/* CONFIG_FSL_MC_ENET */
> > +#endif	/* CONFIG_RESV_RAM */
> >
> 
> CONFIG_FSL_MC_ENET will select the CONFIG_RESV_RAM. What benefit we
> have with this change ?
> because we are reserving memory for MC in the following code, so earlier
> check (with CONFIG_FSL_MC_ENET) looks good to be.

No benefit, but it's not the correct logic, see the change log, so correct.

Thanks,
Zhiqiang

> 
> >  #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
> >  #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> > --
> > 2.17.1
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b443894453..1b7729c046 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1379,7 +1379,7 @@  static int tfa_dram_init_banksize(void)
 	if (i > 0)
 		ret = 0;
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1402,7 +1402,7 @@  static int tfa_dram_init_banksize(void)
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 	return ret;
 }
@@ -1465,7 +1465,7 @@  int dram_init_banksize(void)
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
@@ -1488,7 +1488,7 @@  int dram_init_banksize(void)
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
-#endif	/* CONFIG_FSL_MC_ENET */
+#endif	/* CONFIG_RESV_RAM */
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE