diff mbox series

[v6,017/102] x86: timer: Reduce timer code size in TPL on Intel CPUs

Message ID 20191206213936.v6.17.Iad80fbb5c71f5f28b18ecfad429abf9f41cfb23f@changeid
State Accepted
Commit 642e8487ec629b43b1c5caf846098bfc952be5c0
Delegated to: Bin Meng
Headers show
Series x86: Add initial support for apollolake | expand

Commit Message

Simon Glass Dec. 7, 2019, 4:41 a.m. UTC
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as

   39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message to indicate that CPU-identity bug is fixed

Changes in v3: None
Changes in v2: None

 drivers/timer/Kconfig     | 9 +++++++++
 drivers/timer/tsc_timer.c | 7 +++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

Comments

Bin Meng Dec. 8, 2019, 2:41 a.m. UTC | #1
On Sat, Dec 7, 2019 at 12:46 PM Simon Glass <sjg@chromium.org> wrote:
>
> Most of the timer-calibration methods are not needed on recent Intel CPUs
> and just increase code size. Add an option to use the known-good way to
> get the clock frequency in TPL. Size reduction is about 700 bytes.
>
> Note that version 1 of this commit caused bootstage to crash since the CPU
> was not identified. This is corrected by changes previously applied to
> make sure that the CPU is identified before spl_init() is called, such as
>
>    39146a2e0b x86: Move CPU init to before spl_init()
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4:
> - Update commit message to indicate that CPU-identity bug is fixed
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/timer/Kconfig     | 9 +++++++++
>  drivers/timer/tsc_timer.c | 7 +++++--
>  2 files changed, 14 insertions(+), 2 deletions(-)
>

applied to u-boot-x86/next, thanks!
diff mbox series

Patch

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 41f9755133..96cc49273f 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -188,6 +188,15 @@  config X86_TSC_READ_BASE
 	  The only exception is when U-Boot is used as a secondary bootloader,
 	  where this option should be enabled.
 
+config TPL_X86_TSC_TIMER_NATIVE
+	bool "x86 TSC timer uses native calibration"
+	depends on TPL && X86_TSC_TIMER
+	help
+	  Selects native timer calibration for TPL and don't include the other
+	  methods in the code. This helps to reduce code size in TPL and works
+	  on fairly modern Intel chips. Code-size reductions is about 700
+	  bytes.
+
 config MTK_TIMER
 	bool "MediaTek timer support"
 	depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 813817f467..43cb2d820e 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -50,8 +50,7 @@  static unsigned long native_calibrate_tsc(void)
 		return 0;
 
 	crystal_freq = tsc_info.ecx / 1000;
-
-	if (!crystal_freq) {
+	if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
 		switch (gd->arch.x86_model) {
 		case INTEL_FAM6_SKYLAKE_MOBILE:
 		case INTEL_FAM6_SKYLAKE_DESKTOP:
@@ -407,6 +406,10 @@  static void tsc_timer_ensure_setup(bool early)
 		if (fast_calibrate)
 			goto done;
 
+		/* Reduce code size by dropping other methods */
+		if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
+			panic("no timer");
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;