diff mbox series

[U-Boot,34/42] ls1021aqds: dcu: support dm_i2c_* API

Message ID 20191114103641.34085-34-biwen.li@nxp.com
State Changes Requested
Delegated to: Priyanka Jain
Headers show
Series [U-Boot,01/42] configs: ls1012a: enable CONFIG_DM_I2C | expand

Commit Message

Biwen Li Nov. 14, 2019, 10:36 a.m. UTC
This supports dm_i2c_* API to fix
compilation error when enabled CONFIG_DM_I2C
as follows:
	- board/freescale/ls1021aqds/built-in.o: In function `platform_dcu_init:
	  board/freescale/ls1021aqds/dcu.c:54: undefined reference to `i2c_read'
	  board/freescale/ls1021aqds/dcu.c:63: undefined reference to
	  `i2c_write'
	  board/freescale/ls1021aqds/dcu.c:79: undefined reference to
	  `i2c_set_bus_num'
  `
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
 board/freescale/ls1021aqds/dcu.c | 43 +++++++++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
index c4eac5e302..48953d3b31 100644
--- a/board/freescale/ls1021aqds/dcu.c
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -15,11 +15,23 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int select_i2c_ch_pca9547(u8 ch)
+static int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
 
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -51,6 +63,28 @@  int platform_dcu_init(struct fb_info *fbinfo,
 	u8 ch;
 
 	/* Mux I2C3+I2C4 as HSYNC+VSYNC */
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+
+	/* QIXIS device mount on I2C1 bus*/
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       0);
+		return ret;
+	}
+	ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+	if (ret) {
+		printf("Error: failed to read I2C @%02x\n",
+		       CONFIG_SYS_I2C_QIXIS_ADDR);
+		return ret;
+	}
+	ch &= 0x1F;
+	ch |= 0xA0;
+	ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+
+#else
 	ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
 		       1, &ch, 1);
 	if (ret) {
@@ -62,6 +96,7 @@  int platform_dcu_init(struct fb_info *fbinfo,
 	ch |= 0xA0;
 	ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
 			1, &ch, 1);
+#endif
 	if (ret) {
 		printf("Error: failed to write I2C @%02x\n",
 		       CONFIG_SYS_I2C_QIXIS_ADDR);
@@ -76,10 +111,12 @@  int platform_dcu_init(struct fb_info *fbinfo,
 		pixval = 1000000000 / dcu_fb_videomode->pixclock;
 		pixval *= 1000;
 
+#ifndef CONFIG_DM_I2C
 		i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
-		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+#endif
+		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301, CONFIG_SYS_I2C_DVI_BUS_NUM);
 		diu_set_dvi_encoder(pixval);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, CONFIG_SYS_I2C_DVI_BUS_NUM);
 	} else {
 		return 0;
 	}