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[U-Boot,v10,2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK

Message ID 20190305155349.24367-3-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add support for loading FPGA bitstream | expand

Commit Message

Chee, Tien Fong March 5, 2019, 3:53 p.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Add default fitImage file bundling FPGA bitstreams for Arria10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

---

changes for v10
- Replaced both periph anc core image nodes "@1" and "@2" with "-1",
  the numeric associates the core and periph images in case where there
  are multiple.

changes for v9
- Reordered the images and fpga configurations.
- Removed the load property at core image.

changes for v8
- Changed the FPGA node name to fpga-core and fpga-periph for both core and
  periph bitstreams respectively.
---
 board/altera/arria10-socdk/fit_spl_fpga.its | 38 +++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
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Patch

diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 0000000000..adae997213
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@ 
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA early IO release config";
+			fpga = "fpga-periph-1", "fpga-core-1";
+		};
+	};
+};