From patchwork Tue Mar 5 15:53:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1051810 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44DM1D4R3Vz9s3q for ; Wed, 6 Mar 2019 02:55:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 46762C21DD4; Tue, 5 Mar 2019 15:54:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 285A0C21E35; Tue, 5 Mar 2019 15:54:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AA3FEC21E42; Tue, 5 Mar 2019 15:54:06 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lists.denx.de (Postfix) with ESMTPS id 4A0ABC21D56 for ; Tue, 5 Mar 2019 15:54:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2019 07:54:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,444,1544515200"; d="scan'208";a="149456270" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by fmsmga004.fm.intel.com with ESMTP; 05 Mar 2019 07:53:58 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 5 Mar 2019 23:53:42 +0800 Message-Id: <20190305155349.24367-3-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20190305155349.24367-1-tien.fong.chee@intel.com> References: <20190305155349.24367-1-tien.fong.chee@intel.com> Cc: Marek Vasut , Ching Liang See , Tien Fong Chee , Westergteen Dalon Subject: [U-Boot] [PATCH v10 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v10 - Replaced both periph anc core image nodes "@1" and "@2" with "-1", the numeric associates the core and periph images in case where there are multiple. changes for v9 - Reordered the images and fpga configurations. - Removed the load property at core image. changes for v8 - Changed the FPGA node name to fpga-core and fpga-periph for both core and periph bitstreams respectively. --- board/altera/arria10-socdk/fit_spl_fpga.its | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000000..adae997213 --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation + * + */ + +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +};