| Message ID | 20190212165708.23040-3-michael@amarulasolutions.com |
|---|---|
| State | RFC |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | [U-Boot,RFC,1/3] sunxi: Use clrsetbits_le32 instead of multiple instruction | expand |
On Tue, Feb 12, 2019 at 05:57:08PM +0100, Michael Trimarchi wrote: > Set two rank timing and exit self-refresh timing seems not done > properly. Why? Seriously, a commit log isn't there to vaguely describe whatever you're doing. It's there to expose what precise issue you faced, and how you overcame it. Maxime
Hi Maxime On Wed, Feb 13, 2019 at 9:45 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > On Tue, Feb 12, 2019 at 05:57:08PM +0100, Michael Trimarchi wrote: > > Set two rank timing and exit self-refresh timing seems not done > > properly. > > Why? > > Seriously, a commit log isn't there to vaguely describe whatever > you're doing. It's there to expose what precise issue you faced, and > how you overcame it. I have no documentation, I know only the result. Test was cycling booting from FEL over usb. I was having on some sample 30% of failure and now I have 100% of success. Michael > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com
On Wed, Feb 13, 2019 at 09:50:44AM +0100, Michael Nazzareno Trimarchi wrote: > Hi Maxime > > On Wed, Feb 13, 2019 at 9:45 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > > > On Tue, Feb 12, 2019 at 05:57:08PM +0100, Michael Trimarchi wrote: > > > Set two rank timing and exit self-refresh timing seems not done > > > properly. > > > > Why? > > > > Seriously, a commit log isn't there to vaguely describe whatever > > you're doing. It's there to expose what precise issue you faced, and > > how you overcame it. > > I have no documentation, I know only the result. Test was cycling booting > from FEL over usb. I was having on some sample 30% of failure and now > I have 100% of success. Well, that's still a pretty good information to give. On which boards, with which DRAM setup? with which SoC? etc. Maxime
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index d73a93a132..355fe30aba 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -146,7 +146,7 @@ static void auto_set_timing_para(struct dram_para *para) writel(reg_val, &mctl_ctl->dramtmg5); /* Set two rank timing and exit self-refresh timing */ clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0), - 0x33 << 8 | (0x8 << 0)); + 0x33 << 8 | (0x10 << 0)); /* Set phy interface time */ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | (wr_latency << 0);
Set two rank timing and exit self-refresh timing seems not done properly. We know use the same write that we are using on H5 silicon. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)