| Message ID | 20170214144714.96516-3-andriy.shevchenko@linux.intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
Hi Andy, On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > There is no microcode update available for SoCs used on Intel MID > platforms. > > Use conditional to bypass it. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > --- > arch/x86/cpu/mp_init.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c > index 988073cc79..4e2f000f75 100644 > --- a/arch/x86/cpu/mp_init.c > +++ b/arch/x86/cpu/mp_init.c > @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) > if (!stack) > return -ENOMEM; > params->stack_top = (u32)(stack + size); > -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) > +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && !defined(CONFIG_INTEL_MID) > params->microcode_ptr = ucode_base; > debug("Microcode at %x\n", params->microcode_ptr); > #endif Is this patch necessary? If Intel MID does not define CONFIG_QEMU or CONFIG_HAVE_FSP, current logic should work. Regards, Bin
On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote: > Hi Andy, > > On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko > <andriy.shevchenko@linux.intel.com> wrote: > > There is no microcode update available for SoCs used on Intel MID > > platforms. > > > > Use conditional to bypass it. > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > --- > > arch/x86/cpu/mp_init.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c > > index 988073cc79..4e2f000f75 100644 > > --- a/arch/x86/cpu/mp_init.c > > +++ b/arch/x86/cpu/mp_init.c > > @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t > > **ap_countp, int num_cpus) > > if (!stack) > > return -ENOMEM; > > params->stack_top = (u32)(stack + size); > > -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) > > +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && > > !defined(CONFIG_INTEL_MID) > > params->microcode_ptr = ucode_base; > > debug("Microcode at %x\n", params->microcode_ptr); > > #endif > > Is this patch necessary? If Intel MID does not define CONFIG_QEMU or > CONFIG_HAVE_FSP, current logic should work. This code is executed when neither of option is defined. For Intel MID we do *not* need to have this code executed. I dunno how it possible can work otherwise (ucode_base is not defined).
On 14 February 2017 at 07:47, Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > There is no microcode update available for SoCs used on Intel MID > platforms. > > Use conditional to bypass it. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > --- > arch/x86/cpu/mp_init.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass <sjg@chromium.org>
Hi Andy, On Wed, Feb 15, 2017 at 5:52 PM, Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote: >> Hi Andy, >> >> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko >> <andriy.shevchenko@linux.intel.com> wrote: >> > There is no microcode update available for SoCs used on Intel MID >> > platforms. >> > >> > Use conditional to bypass it. >> > >> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> >> > --- >> > arch/x86/cpu/mp_init.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c >> > index 988073cc79..4e2f000f75 100644 >> > --- a/arch/x86/cpu/mp_init.c >> > +++ b/arch/x86/cpu/mp_init.c >> > @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t >> > **ap_countp, int num_cpus) >> > if (!stack) >> > return -ENOMEM; >> > params->stack_top = (u32)(stack + size); >> > -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) >> > +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && >> > !defined(CONFIG_INTEL_MID) >> > params->microcode_ptr = ucode_base; >> > debug("Microcode at %x\n", params->microcode_ptr); >> > #endif >> >> Is this patch necessary? If Intel MID does not define CONFIG_QEMU or >> CONFIG_HAVE_FSP, current logic should work. > > This code is executed when neither of option is defined. For Intel MID > we do *not* need to have this code executed. > > I dunno how it possible can work otherwise (ucode_base is not defined). > OK, is this common feature for all Intel MID device? This mp_init.c is conditionally built by CONFIG_SMP. So I believe this Tangier SoC is a multi-core processor, but does not have any microcode. Regards, Bin
On Fri, Feb 17, 2017 at 3:22 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Wed, Feb 15, 2017 at 5:52 PM, Andy Shevchenko > <andriy.shevchenko@linux.intel.com> wrote: >> On Wed, 2017-02-15 at 11:10 +0800, Bin Meng wrote: >>> On Tue, Feb 14, 2017 at 10:47 PM, Andy Shevchenko >>> <andriy.shevchenko@linux.intel.com> wrote: >> This code is executed when neither of option is defined. For Intel MID >> we do *not* need to have this code executed. >> >> I dunno how it possible can work otherwise (ucode_base is not defined). > OK, is this common feature for all Intel MID device? This mp_init.c is > conditionally built by CONFIG_SMP. So I believe this Tangier SoC is a > multi-core processor, but does not have any microcode. Correct. I will leave this patch as is in v3 which I'm about to submit.
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 988073cc79..4e2f000f75 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && !defined(CONFIG_INTEL_MID) params->microcode_ptr = ucode_base; debug("Microcode at %x\n", params->microcode_ptr); #endif
There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- arch/x86/cpu/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)