| Message ID | 20160909134412.24643-5-paul.burton@imgtec.com |
|---|---|
| State | Superseded |
| Delegated to: | Daniel Schwierzeck |
| Headers | show |
Am 09.09.2016 um 15:44 schrieb Paul Burton: > Enable use of the instruction cache immediately after it has been > initialised. This will only take effect if U-Boot was linked to run from > kseg0 rather than kseg1, but when this is the case the data cache > initialisation code will run cached & thus significantly faster. Could you have a look at an experimental patch queue [1] for an updated MIPS startup. I've started this some months ago but hadn't time to finish it nor to test it on real hardware. Some parts are inspired by the Imgtec's MIPS boot example code. I've rebased the branch to current u-boot-mips/next and it works at least with Malta in Qemu. Basically the changes regarding caches are: - remove CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD because that's only used on the old MIPS boards which didn't see maintenance in years - fix initialization of CP0 registers - split mips_cache_reset() in icache_init() and dcache_init() and enable the caches directly after icache_init() Do you think it makes sense to split mips_cache_reset() in that way? [1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_startup_v1 > > Signed-off-by: Paul Burton <paul.burton@imgtec.com> > --- > > Changes in v2: None > > arch/mips/cpu/start.S | 8 -------- > arch/mips/lib/cache_init.S | 12 ++++++++++++ > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S > index fc6dd66..827a544 100644 > --- a/arch/mips/cpu/start.S > +++ b/arch/mips/cpu/start.S > @@ -12,10 +12,6 @@ > #include <asm/regdef.h> > #include <asm/mipsregs.h> > > -#ifndef CONFIG_SYS_MIPS_CACHE_MODE > -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT > -#endif > - > #ifndef CONFIG_SYS_INIT_SP_ADDR > #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ > CONFIG_SYS_INIT_SP_OFFSET) > @@ -154,10 +150,6 @@ reset: > PTR_LA t9, mips_cache_reset > jalr t9 > nop > - > - /* ... and enable them */ > - li t0, CONFIG_SYS_MIPS_CACHE_MODE > - mtc0 t0, CP0_CONFIG > #endif > > /* Set up temporary stack */ > diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S > index bc8ab27..c3fb249 100644 > --- a/arch/mips/lib/cache_init.S > +++ b/arch/mips/lib/cache_init.S > @@ -172,6 +172,18 @@ LEAF(mips_cache_reset) > cache_loop t0, t1, t8, INDEX_STORE_TAG_I > #endif > > + /* Enable use of the I-cache by setting Config.K0 */ > + mfc0 t0, CP0_CONFIG > + li t1, CONFIG_SYS_MIPS_CACHE_MODE > +#if __mips_isa_rev >= 2 > + ins t0, t1, 0, 3 > +#else > + ori t0, t0, CONF_CM_CMASK > + xori t0, t0, CONF_CM_CMASK > + or t0, t0, t1 > +#endif > + mtc0 t0, CP0_CONFIG > + > /* > * then initialize D-cache. > */ >
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index fc6dd66..827a544 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,10 +12,6 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) @@ -154,10 +150,6 @@ reset: PTR_LA t9, mips_cache_reset jalr t9 nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG #endif /* Set up temporary stack */ diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index bc8ab27..c3fb249 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -172,6 +172,18 @@ LEAF(mips_cache_reset) cache_loop t0, t1, t8, INDEX_STORE_TAG_I #endif + /* Enable use of the I-cache by setting Config.K0 */ + mfc0 t0, CP0_CONFIG + li t1, CONFIG_SYS_MIPS_CACHE_MODE +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 +#endif + mtc0 t0, CP0_CONFIG + /* * then initialize D-cache. */
Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v2: None arch/mips/cpu/start.S | 8 -------- arch/mips/lib/cache_init.S | 12 ++++++++++++ 2 files changed, 12 insertions(+), 8 deletions(-)