From patchwork Fri Sep 9 13:44:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 668053 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sVz4b4FJWz9ryn for ; Fri, 9 Sep 2016 23:46:07 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDBDCA7548; Fri, 9 Sep 2016 15:45:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L_Vg0kYFCZSt; Fri, 9 Sep 2016 15:45:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BFB74B9AD; Fri, 9 Sep 2016 15:45:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1AEA14B9AD for ; Fri, 9 Sep 2016 15:45:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id k9BWl78mJDXx for ; Fri, 9 Sep 2016 15:45:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailapp01.imgtec.com (mailapp01.imgtec.com [195.59.15.196]) by theia.denx.de (Postfix) with ESMTP id E52A74B77D for ; Fri, 9 Sep 2016 15:45:46 +0200 (CEST) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id B35C030F08DEF; Fri, 9 Sep 2016 14:45:32 +0100 (IST) Received: from localhost (10.100.200.46) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 9 Sep 2016 14:45:35 +0100 From: Paul Burton To: , Daniel Schwierzeck Date: Fri, 9 Sep 2016 14:44:06 +0100 Message-ID: <20160909134412.24643-5-paul.burton@imgtec.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160909134412.24643-1-paul.burton@imgtec.com> References: <20160909134412.24643-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.46] Cc: Purna Chandra Mandal Subject: [U-Boot] [PATCH v2 04/10] MIPS: Enable use of the instruction cache earlier X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton --- Changes in v2: None arch/mips/cpu/start.S | 8 -------- arch/mips/lib/cache_init.S | 12 ++++++++++++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index fc6dd66..827a544 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -12,10 +12,6 @@ #include #include -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) @@ -154,10 +150,6 @@ reset: PTR_LA t9, mips_cache_reset jalr t9 nop - - /* ... and enable them */ - li t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG #endif /* Set up temporary stack */ diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index bc8ab27..c3fb249 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -172,6 +172,18 @@ LEAF(mips_cache_reset) cache_loop t0, t1, t8, INDEX_STORE_TAG_I #endif + /* Enable use of the I-cache by setting Config.K0 */ + mfc0 t0, CP0_CONFIG + li t1, CONFIG_SYS_MIPS_CACHE_MODE +#if __mips_isa_rev >= 2 + ins t0, t1, 0, 3 +#else + ori t0, t0, CONF_CM_CMASK + xori t0, t0, CONF_CM_CMASK + or t0, t0, t1 +#endif + mtc0 t0, CP0_CONFIG + /* * then initialize D-cache. */