Message ID | 1644578217-8947-1-git-send-email-haibo.chen@nxp.com |
---|---|
State | Superseded |
Delegated to: | Jaehoon Chung |
Headers | show |
Series | [1/3] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary | expand |
On 2/11/22 12:16, haibo.chen@nxp.com wrote: Hi, [...] > @@ -897,6 +900,11 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) > > esdhc_stop_tuning(mmc); > > + /* change to default setting, let host control the card clock */ > + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > + if (readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100)) Please propagate the error in both cases: ret = readx_poll..(); if (ret) dev_warn(...); return ret; > + pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n"); btw. s@gate@gated@ , s@expect@expected@ (past tense) With those small details fixed: Reviewed-by: Marek Vasut <marex@denx.de>
Hi Fabio, Can you help test these 3 patches on imx6qdl-pico board or imx7s board on your side to double check whether these patches enlarge the total boot time? Best Regards Bough Chen > -----Original Message----- > From: Marek Vasut [mailto:marex@denx.de] > Sent: 2022年2月14日 5:53 > To: Bough Chen <haibo.chen@nxp.com>; Peng Fan <peng.fan@nxp.com>; > jh80.chung@samsung.com; festevam@gmail.com; sean.anderson@seco.com; > u-boot@lists.denx.de; aford173@gmail.com; tharvey@gateworks.com; > andrey.zhizhikin@leica-geosystems.com > Cc: dl-uboot-imx <uboot-imx@nxp.com> > Subject: Re: [PATCH 1/3] mmc: fsl_esdhc_imx: use > VENDORSPEC_FRC_SDCLK_ON when necessary > > On 2/11/22 12:16, haibo.chen@nxp.com wrote: > > Hi, > > [...] > > > @@ -897,6 +900,11 @@ static int fsl_esdhc_execute_tuning(struct udevice > *dev, uint32_t opcode) > > > > esdhc_stop_tuning(mmc); > > > > + /* change to default setting, let host control the card clock */ > > + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > > + if (readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & > PRSSTAT_SDOFF, 100)) > > Please propagate the error in both cases: > > ret = readx_poll..(); > if (ret) > dev_warn(...); > > return ret; > > > + pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n"); > > btw. s@gate@gated@ , s@expect@expected@ (past tense) > > With those small details fixed: > > Reviewed-by: Marek Vasut <marex@denx.de>
Hi Bough, On Sun, Feb 13, 2022 at 11:58 PM Bough Chen <haibo.chen@nxp.com> wrote: > > Hi Fabio, > > Can you help test these 3 patches on imx6qdl-pico board or imx7s board on your side to double check whether these patches enlarge the total boot time? I have tested the series on an imx7s-warp and the previous issue of slow boot is no longer present, thanks: Tested-by: Fabio Estevam <festevam@gmail.com>
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 9299635f50..362e3e13b6 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -832,12 +832,15 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) u32 irqstaten = esdhc_read32(®s->irqstaten); u32 irqsigen = esdhc_read32(®s->irqsigen); int i, ret = -ETIMEDOUT; - u32 val, mixctrl; + u32 val, mixctrl, tmp; /* clock tuning is not needed for upto 52MHz */ if (mmc->clock <= 52000000) return 0; + /* make sure the card clock keep on */ + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ if (priv->flags & ESDHC_FLAG_STD_TUNING) { val = esdhc_read32(®s->autoc12err); @@ -897,6 +900,11 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) esdhc_stop_tuning(mmc); + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + if (readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100)) + pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n"); + return ret; } #endif @@ -1560,9 +1568,18 @@ static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, struct fsl_esdhc_priv *priv = dev_get_priv(dev); struct fsl_esdhc *regs = priv->esdhc_regs; + /* make sure the card clock keep on */ + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, !!(tmp & PRSSTAT_DAT0) == !!state, timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + if (readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100)) + pr_warn("fsl_esdhc_imx: card clock not gate off as expect.\n"); + return ret; } diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 2153f29bef..b8efd2a166 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -37,6 +37,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -94,6 +95,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002)