diff mbox series

[2/3] mmc: fsl_esdhc_imx: remove redundant ARCH_MXC

Message ID 1644578217-8947-2-git-send-email-haibo.chen@nxp.com
State Accepted
Commit 45254edd9415df2923098f960b8e4d05aea24b74
Delegated to: Jaehoon Chung
Headers show
Series [1/3] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary | expand

Commit Message

Bough Chen Feb. 11, 2022, 11:16 a.m. UTC 
From: Haibo Chen <haibo.chen@nxp.com>

Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c.
fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mmc/fsl_esdhc_imx.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

Comments

Marek Vasut Feb. 13, 2022, 9:53 p.m. UTC | #1 
On 2/11/22 12:16, haibo.chen@nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
> 
> Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c.
> fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant.

Reviewed-by: Marek Vasut <marex@denx.de>
Stefano Babic Feb. 19, 2022, 1:07 p.m. UTC | #2 
> From: Haibo Chen <haibo.chen@nxp.com>
> Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c.
> fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant.
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 362e3e13b6..0be7cae1e5 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -596,16 +596,12 @@  static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 	int sdhc_clk = priv->sdhc_clk;
 	uint clk;
 
-	if (IS_ENABLED(ARCH_MXC)) {
 #if IS_ENABLED(CONFIG_MX53)
-		/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
-		pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+	pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
 #else
-		pre_div = 1;
+	pre_div = 1;
 #endif
-	} else {
-		pre_div = 2;
-	}
 
 	while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
 		pre_div *= 2;
@@ -1016,11 +1012,6 @@  static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 		esdhc_write32(&regs->dllctrl, 0x0);
 	}
 
-#ifndef ARCH_MXC
-	/* Enable cache snooping */
-	esdhc_write32(&regs->scr, 0x00000040);
-#endif
-
 	if (IS_ENABLED(CONFIG_FSL_USDHC))
 		esdhc_setbits32(&regs->vendorspec,
 				VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);