Message ID | 1517660371-22013-1-git-send-email-david.wu@rock-chips.com |
---|---|
State | Changes Requested |
Delegated to: | Philipp Tomsich |
Headers | show |
Series | Add integrated phy support for rk322x and rk3328 | expand |
> There is a wrong selection for gmac pll source, fix it. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > drivers/clk/rockchip/clk_rk322x.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> There is a wrong selection for gmac pll source, fix it. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > drivers/clk/rockchip/clk_rk322x.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4bbcaf8..72c8757 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -255,7 +255,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) ulong pll_rate; u8 div; - if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) + if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else /* CPLL is not set */
There is a wrong selection for gmac pll source, fix it. Signed-off-by: David Wu <david.wu@rock-chips.com> --- drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)