From patchwork Sat Feb 3 12:16:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868887 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXvp0zj6z9t5s for ; Sat, 3 Feb 2018 23:19:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 45C45C21E45; Sat, 3 Feb 2018 12:17:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 016C7C21DED; Sat, 3 Feb 2018 12:17:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BBF76C21C2F; Sat, 3 Feb 2018 12:16:58 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.137]) by lists.denx.de (Postfix) with ESMTPS id 7990DC21C51 for ; Sat, 3 Feb 2018 12:16:57 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by regular1.263xmail.com (Postfix) with ESMTP id 34D93DA39; Sat, 3 Feb 2018 20:16:51 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 01CEB381; Sat, 3 Feb 2018 20:16:52 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith SMTP id 6626M8BFYI; Sat, 03 Feb 2018 20:16:53 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:16:33 +0800 Message-Id: <1517660196-21802-2-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 01/14] net: rockchip: Separate rmii and rgmii speed setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some Socs both have rgmii and rmii interface, so we need to separate their speed setting. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/net/gmac_rockchip.c | 62 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 19 deletions(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 683e820..4396ca1 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -40,7 +40,10 @@ struct gmac_rockchip_platdata { }; struct rk_gmac_ops { - int (*fix_mac_speed)(struct dw_eth_dev *priv); + int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv); + int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv); void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); } -static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk322x_grf *grf; int clk; @@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3288_grf *grf; int clk; @@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } -static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3328_grf_regs *grf; int clk; @@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3368_grf *grf; int clk; @@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3399_grf_regs *grf; int clk; @@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } -static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rv1108_grf *grf; int clk, speed; @@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev) break; default: - debug("NO interface defined!\n"); + debug("%s: NO interface defined!\n", __func__); return -ENXIO; } @@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev) static int gmac_rockchip_eth_start(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); int ret; - ret = designware_eth_init(priv, pdata->enetaddr); - if (ret) - return ret; - ret = ops->fix_mac_speed(priv); + ret = designware_eth_init(priv, eth_pdata->enetaddr); if (ret) return ret; + + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = ops->fix_rgmii_speed(pdata, priv); + if (ret) + return ret; + break; + case PHY_INTERFACE_MODE_RMII: + ret = ops->fix_rmii_speed(pdata, priv); + if (ret) + return ret; + break; + default: + debug("%s: NO interface defined!\n", __func__); + return -ENXIO; + } + ret = designware_eth_enable(priv); if (ret) return ret; @@ -527,32 +551,32 @@ const struct eth_ops gmac_rockchip_eth_ops = { }; const struct rk_gmac_ops rk3228_gmac_ops = { - .fix_mac_speed = rk3228_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rgmii = rk3228_gmac_set_to_rgmii, }; const struct rk_gmac_ops rk3288_gmac_ops = { - .fix_mac_speed = rk3288_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, }; const struct rk_gmac_ops rk3328_gmac_ops = { - .fix_mac_speed = rk3328_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rgmii = rk3328_gmac_set_to_rgmii, }; const struct rk_gmac_ops rk3368_gmac_ops = { - .fix_mac_speed = rk3368_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii, }; const struct rk_gmac_ops rk3399_gmac_ops = { - .fix_mac_speed = rk3399_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, .set_to_rgmii = rk3399_gmac_set_to_rgmii, }; const struct rk_gmac_ops rv1108_gmac_ops = { - .fix_mac_speed = rv1108_set_rmii_speed, + .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, .set_to_rmii = rv1108_gmac_set_to_rmii, }; From patchwork Sat Feb 3 12:16:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868888 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXwC65vHz9t5s for ; Sat, 3 Feb 2018 23:19:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 73344C21D9F; Sat, 3 Feb 2018 12:17:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1EB4CC21E3A; Sat, 3 Feb 2018 12:17:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 12256C21E16; Sat, 3 Feb 2018 12:17:00 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.141]) by lists.denx.de (Postfix) with ESMTPS id 43AAAC21C2F for ; Sat, 3 Feb 2018 12:16:59 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by regular1.263xmail.com (Postfix) with ESMTP id 3C4DE5F; Sat, 3 Feb 2018 20:16:55 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id CF457381; Sat, 3 Feb 2018 20:16:54 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith SMTP id 6626MGLZHH; Sat, 03 Feb 2018 20:16:55 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:16:34 +0800 Message-Id: <1517660196-21802-3-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 02/14] net: rockchip: Add rmii interface and rmii speed setup for rk3228 and rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rk3228 and rk3328 Socs both have rmii interface, that might be used, so add them for usage. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/net/gmac_rockchip.c | 115 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 4396ca1..5afc415 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -73,6 +73,41 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); } +static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) +{ + struct rk322x_grf *grf; + int clk; + enum { + RK3228_GMAC_RMII_CLK_MASK = BIT(7), + RK3228_GMAC_RMII_CLK_2_5M = 0, + RK3228_GMAC_RMII_CLK_25M = BIT(7), + + RK3228_GMAC_RMII_SPEED_MASK = BIT(2), + RK3228_GMAC_RMII_SPEED_10 = 0, + RK3228_GMAC_RMII_SPEED_100 = BIT(2), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10; + break; + case 100: + clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK, + clk); + + return 0; +} + static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, struct dw_eth_dev *priv) { @@ -134,6 +169,41 @@ static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, return 0; } +static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) +{ + struct rk3328_grf_regs *grf; + int clk; + enum { + RK3328_GMAC_RMII_CLK_MASK = BIT(7), + RK3328_GMAC_RMII_CLK_2_5M = 0, + RK3328_GMAC_RMII_CLK_25M = BIT(7), + + RK3328_GMAC_RMII_SPEED_MASK = BIT(2), + RK3328_GMAC_RMII_SPEED_10 = 0, + RK3328_GMAC_RMII_SPEED_100 = BIT(2), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10; + break; + case 100: + clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], + RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK, + clk); + + return 0; +} + static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, struct dw_eth_dev *priv) { @@ -264,6 +334,28 @@ static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, return 0; } +static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), + RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), + RK3228_RMII_MODE_MASK = BIT(10), + RK3228_RMII_MODE_SEL = BIT(10), + RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_GRF_CON_RMII_MODE_MASK | + RK3228_RMII_MODE_MASK | + RK3228_GMAC_PHY_INTF_SEL_MASK, + RK3228_GRF_CON_RMII_MODE_SEL | + RK3228_RMII_MODE_SEL | + RK3228_GMAC_PHY_INTF_SEL_RMII); +} + static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk322x_grf *grf; @@ -328,6 +420,25 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_RMII_MODE_MASK = BIT(9), + RK3328_RMII_MODE = BIT(9), + + RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], + RK3328_RMII_MODE_MASK | + RK3328_GMAC_PHY_INTF_SEL_MASK, + RK3328_GMAC_PHY_INTF_SEL_RMII | + RK3328_RMII_MODE); +} + static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3328_grf_regs *grf; @@ -551,7 +662,9 @@ const struct eth_ops gmac_rockchip_eth_ops = { }; const struct rk_gmac_ops rk3228_gmac_ops = { + .fix_rmii_speed = rk3228_gmac_fix_rmii_speed, .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, + .set_to_rmii = rk3228_gmac_set_to_rmii, .set_to_rgmii = rk3228_gmac_set_to_rgmii, }; @@ -561,7 +674,9 @@ const struct rk_gmac_ops rk3288_gmac_ops = { }; const struct rk_gmac_ops rk3328_gmac_ops = { + .fix_rmii_speed = rk3328_gmac_fix_rmii_speed, .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, + .set_to_rmii = rk3328_gmac_set_to_rmii, .set_to_rgmii = rk3328_gmac_set_to_rgmii, }; From patchwork Sat Feb 3 12:16:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868889 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXxQ3nh0z9t5s for ; Sat, 3 Feb 2018 23:20:26 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E30C1C21E18; Sat, 3 Feb 2018 12:18:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4E96CC21DD9; Sat, 3 Feb 2018 12:17:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AA5EFC21E5A; Sat, 3 Feb 2018 12:17:04 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.139]) by lists.denx.de (Postfix) with ESMTPS id D2B90C21C8F for ; Sat, 3 Feb 2018 12:16:59 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by regular1.263xmail.com (Postfix) with ESMTP id A719D543F; Sat, 3 Feb 2018 20:16:54 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 5DF2F3A6; Sat, 3 Feb 2018 20:16:56 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <318aa1b7637c6cb6ee4be864fc7ef109> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith SMTP id 66260AKIGS; Sat, 03 Feb 2018 20:16:57 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:16:35 +0800 Message-Id: <1517660196-21802-4-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 03/14] net: rockchip: Add integrated phy ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some rockchio Socs have integrated phy inside, to support it, add the integrated phy ops. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/net/gmac_rockchip.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 5afc415..bca0a2a 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include "designware.h" @@ -35,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; struct gmac_rockchip_platdata { struct dw_eth_pdata dw_eth_pdata; bool clock_input; + bool integrated_phy; + struct reset_ctl phy_reset; int tx_delay; int rx_delay; }; @@ -46,13 +50,16 @@ struct rk_gmac_ops { struct dw_eth_dev *priv); void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); + void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); }; static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + struct ofnode_phandle_args args; const char *string; + int ret; string = dev_read_string(dev, "clock_in_out"); if (!strcmp(string, "input")) @@ -60,6 +67,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) else pdata->clock_input = false; + /* If phy-handle property is passed from DT, use it as the PHY */ + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); + if (ret) { + debug("Cannot get phy phandle: ret=%d\n", ret); + pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); + } else { + debug("Found phy-handle subnode\n"); + pdata->integrated_phy = ofnode_read_bool(args.node, + "phy-is-integrated"); + } + + if (pdata->integrated_phy) { + ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); + if (ret) { + debug("No PHY reset control found: ret=%d\n", ret); + return ret; + } + } + /* Check the new naming-style first... */ pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); @@ -572,6 +598,9 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret; + if (pdata->integrated_phy && ops->integrated_phy_powerup) + ops->integrated_phy_powerup(pdata); + switch (eth_pdata->phy_interface) { case PHY_INTERFACE_MODE_RGMII: /* From patchwork Sat Feb 3 12:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868890 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXxY4RZNz9t5s for ; Sat, 3 Feb 2018 23:20:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3D605C21E26; Sat, 3 Feb 2018 12:18:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27062C21E45; Sat, 3 Feb 2018 12:17:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3439FC21E39; Sat, 3 Feb 2018 12:17:07 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.137]) by lists.denx.de (Postfix) with ESMTPS id BFA9FC21E35 for ; Sat, 3 Feb 2018 12:17:01 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by regular1.263xmail.com (Postfix) with ESMTP id 4335DDAC4; Sat, 3 Feb 2018 20:16:56 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C976A381; Sat, 3 Feb 2018 20:16:57 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <58ac5587ff3d87cfdd83ce43d59f313a> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith SMTP id 6626RH04OX; Sat, 03 Feb 2018 20:16:58 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:16:36 +0800 Message-Id: <1517660196-21802-5-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 04/14] net: rockchip: Add integrated phy for rk3228 and rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rk3228 and rk3328 Socs both support integrated phy, implement their power up function to support it. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/net/gmac_rockchip.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index bca0a2a..ec47933 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -583,6 +583,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) RV1108_GMAC_PHY_INTF_SEL_RMII); } +static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), + }; + enum { + RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3228_MACPHY_CFG_CLK_50M = BIT(14), + + RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3228_MACPHY_RMII_MODE = BIT(6), + + RK3228_MACPHY_ENABLE_MASK = BIT(0), + RK3228_MACPHY_DISENABLE = 0, + RK3228_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->con_iomux, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); + + rk_clrsetreg(&grf->macphy_con[2], + RK3228_RK_GRF_CON2_MACPHY_ID_MASK, + RK3228_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3228_RK_GRF_CON3_MACPHY_ID_MASK, + RK3228_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_CFG_CLK_50M_MASK | + RK3228_MACPHY_RMII_MODE_MASK | + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_CFG_CLK_50M | + RK3228_MACPHY_RMII_MODE | + RK3228_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_ENABLE); + udelay(30 * 1000); +} + +static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), + RK3328_GRF_CON_RMII_MODE = BIT(9), + }; + enum { + RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3328_MACPHY_CFG_CLK_50M = BIT(14), + + RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3328_MACPHY_RMII_MODE = BIT(6), + + RK3328_MACPHY_ENABLE_MASK = BIT(0), + RK3328_MACPHY_DISENABLE = 0, + RK3328_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->macphy_con[1], + RK3328_GRF_CON_RMII_MODE_MASK, + RK3328_GRF_CON_RMII_MODE); + + rk_clrsetreg(&grf->macphy_con[2], + RK3328_RK_GRF_CON2_MACPHY_ID_MASK, + RK3328_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3328_RK_GRF_CON3_MACPHY_ID_MASK, + RK3328_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_CFG_CLK_50M_MASK | + RK3328_MACPHY_RMII_MODE_MASK | + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_CFG_CLK_50M | + RK3328_MACPHY_RMII_MODE | + RK3328_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_ENABLE); + udelay(30 * 1000); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); @@ -695,6 +815,7 @@ const struct rk_gmac_ops rk3228_gmac_ops = { .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rmii = rk3228_gmac_set_to_rmii, .set_to_rgmii = rk3228_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, }; const struct rk_gmac_ops rk3288_gmac_ops = { @@ -707,6 +828,7 @@ const struct rk_gmac_ops rk3328_gmac_ops = { .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rmii = rk3328_gmac_set_to_rmii, .set_to_rgmii = rk3328_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, }; const struct rk_gmac_ops rk3368_gmac_ops = { From patchwork Sat Feb 3 12:18:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868891 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXxy0827z9t5s for ; Sat, 3 Feb 2018 23:20:52 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6A144C21DD7; Sat, 3 Feb 2018 12:19:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B1E91C21E18; Sat, 3 Feb 2018 12:19:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 41FDCC21E39; Sat, 3 Feb 2018 12:19:06 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138]) by lists.denx.de (Postfix) with ESMTPS id 11F85C21E4D for ; Sat, 3 Feb 2018 12:19:05 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.227]) by regular1.263xmail.com (Postfix) with ESMTP id E1FAB78F6; Sat, 3 Feb 2018 20:18:58 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 52E75383; Sat, 3 Feb 2018 20:19:00 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <5f31bd46ec4c9ef02ef444e29af0e8e5> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 3988K22G0F; Sat, 03 Feb 2018 20:19:00 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:18:54 +0800 Message-Id: <1517660334-21937-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 05/14] cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always should not been active. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 4 ++-- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3328.c | 4 ++-- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/rockchip/clk_rv1108.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 510a00a..3c74189 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -347,7 +347,7 @@ static int rk3036_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3036_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 9); if (ret) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4e6d2f0..4bbcaf8 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -509,9 +509,9 @@ static int rk322x_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk322x_cru, cru_softrst_con[0]); - ret = rockchip_reset_bind(dev, ret, 9); + ret = rockchip_reset_bind(dev, ret, 63); if (ret) debug("Warning: software reset driver bind faile\n"); #endif diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 552a71a..0c6b14b 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -968,7 +968,7 @@ static int rk3288_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 12); if (ret) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 2ccc798..3f8cdc0 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -792,9 +792,9 @@ static int rk3328_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3328_cru, softrst_con[0]); - ret = rockchip_reset_bind(dev, ret, 12); + ret = rockchip_reset_bind(dev, ret, 100); if (ret) debug("Warning: software reset driver bind faile\n"); #endif diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3ac9add..bde3635 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -622,7 +622,7 @@ static int rk3368_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3368_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 15); if (ret) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 42926ba..a0fc329 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1320,7 +1320,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) static int rk3399_pmuclk_bind(struct udevice *dev) { -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) int ret; ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 224c813..a2a1223 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -240,7 +240,7 @@ static int rv1108_clk_bind(struct udevice *dev) sys_child->priv = priv; } -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3368_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 13); if (ret) From patchwork Sat Feb 3 12:19:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868892 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXyw1RLnz9t5s for ; Sat, 3 Feb 2018 23:21:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C1423C21E2F; Sat, 3 Feb 2018 12:21:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 11FABC21C4F; Sat, 3 Feb 2018 12:21:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CB4FFC21E26; Sat, 3 Feb 2018 12:19:44 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.132]) by lists.denx.de (Postfix) with ESMTPS id 1A443C21E35 for ; Sat, 3 Feb 2018 12:19:40 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.171]) by regular1.263xmail.com (Postfix) with ESMTP id AABC09370; Sat, 3 Feb 2018 20:19:34 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 4B04B323; Sat, 3 Feb 2018 20:19:34 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 10004SR6E79; Sat, 03 Feb 2018 20:19:36 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:19:31 +0800 Message-Id: <1517660371-22013-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 06/14] clk: rockchip: fix the gmac selection of pll source for rk322x X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is a wrong selection for gmac pll source, fix it. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4bbcaf8..72c8757 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -255,7 +255,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) ulong pll_rate; u8 div; - if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) + if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else /* CPLL is not set */ From patchwork Sat Feb 3 12:20:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868894 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY0S1z2Sz9t5s for ; Sat, 3 Feb 2018 23:23:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D713BC21D56; Sat, 3 Feb 2018 12:21:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 02291C21E39; Sat, 3 Feb 2018 12:21:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9BBF3C21E45; Sat, 3 Feb 2018 12:20:45 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.137]) by lists.denx.de (Postfix) with ESMTPS id 4FE32C21E40 for ; Sat, 3 Feb 2018 12:20:44 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.192]) by regular1.263xmail.com (Postfix) with ESMTP id ADA8FDA39; Sat, 3 Feb 2018 20:20:38 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 8720238C; Sat, 3 Feb 2018 20:20:39 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <49a4db2574e5d95df84dc25dcf0fe55c> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 8404I6GNIU; Sat, 03 Feb 2018 20:20:40 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:20:37 +0800 Message-Id: <1517660437-22099-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 07/14] clk: rockchip: Init CPLL 600M for rk322x X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The gmac for integrated phy need 50M clock, it seems that only come from CPLL 600M, the GPLL is not suitable. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + drivers/clk/rockchip/clk_rk322x.c | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index a7999ca..801363d 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -13,6 +13,7 @@ #define APLL_HZ (600 * MHz) #define GPLL_HZ (594 * MHz) +#define CPLL_HZ (600 * MHz) #define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000 diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 72c8757..4022065 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -40,6 +40,7 @@ enum { /* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1); static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -89,11 +90,13 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | - APLL_MODE_SLOW << APLL_MODE_SHIFT); + APLL_MODE_SLOW << APLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT); /* init pll */ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); /* * select apll as cpu/core clock pll source and @@ -166,7 +169,8 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | - APLL_MODE_NORM << APLL_MODE_SHIFT); + APLL_MODE_NORM << APLL_MODE_SHIFT | + CPLL_MODE_NORM << CPLL_MODE_SHIFT); } /* Get pll rate by id */ @@ -258,8 +262,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else - /* CPLL is not set */ - return -EPERM; + pll_rate = CPLL_HZ; div = DIV_ROUND_UP(pll_rate, freq) - 1; if (div <= 0x1f) From patchwork Sat Feb 3 12:20:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868893 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXz70bHxz9t5s for ; Sat, 3 Feb 2018 23:21:54 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 958ECC21DD7; Sat, 3 Feb 2018 12:21:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D7620C21C2F; Sat, 3 Feb 2018 12:21:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AA42AC21DDF; Sat, 3 Feb 2018 12:21:09 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.135]) by lists.denx.de (Postfix) with ESMTPS id 93F5DC21E45 for ; Sat, 3 Feb 2018 12:21:08 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.175]) by regular1.263xmail.com (Postfix) with ESMTP id 21F101D8C4; Sat, 3 Feb 2018 20:21:03 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 2836B308; Sat, 3 Feb 2018 20:21:02 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 21608YY5MNI; Sat, 03 Feb 2018 20:21:04 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:20:58 +0800 Message-Id: <1517660458-22167-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 08/14] clk: rockchip: Add SCLK_MAC_SRC clock rate setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4022065..7276c4a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -390,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC_SRC: case SCLK_MAC: new_rate = rk322x_mac_set_clk(priv->cru, rate); break; From patchwork Sat Feb 3 12:21:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868895 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY1Z6WYGz9t5s for ; Sat, 3 Feb 2018 23:24:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 51E30C21E5A; Sat, 3 Feb 2018 12:22:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0C307C21E37; Sat, 3 Feb 2018 12:22:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1408EC21DDF; Sat, 3 Feb 2018 12:21:47 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.130]) by lists.denx.de (Postfix) with ESMTPS id B32D4C21C8F for ; Sat, 3 Feb 2018 12:21:43 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.236]) by regular1.263xmail.com (Postfix) with ESMTP id 6F0F4AD10; Sat, 3 Feb 2018 20:21:38 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C99B5375; Sat, 3 Feb 2018 20:21:38 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <3d98ef36312af91c09767ee45ecfbaaa> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 149053ES8N7; Sat, 03 Feb 2018 20:21:39 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:21:34 +0800 Message-Id: <1517660494-22234-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 09/14] ARM: dts: rockchip: Add integrated phy reset and clock for rk322x X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To support the integrated phy for rk322x, add their reset and clock property at dtsi level. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- arch/arm/dts/rk322x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 22324f9..b0254a3 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -449,13 +449,13 @@ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; + <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; + "pclk_mac", "clk_macphy"; + resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; rockchip,grf = <&grf>; status = "disabled"; }; From patchwork Sat Feb 3 12:21:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868898 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY425BQBz9t5s for ; Sat, 3 Feb 2018 23:26:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4E7FCC21E48; Sat, 3 Feb 2018 12:23:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 323DAC21E3C; Sat, 3 Feb 2018 12:23:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BE04FC21E1E; Sat, 3 Feb 2018 12:22:10 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.137]) by lists.denx.de (Postfix) with ESMTPS id B4B6AC21C41 for ; Sat, 3 Feb 2018 12:22:04 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.171]) by regular1.263xmail.com (Postfix) with ESMTP id 35F1FDB3D; Sat, 3 Feb 2018 20:21:59 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 22C02369; Sat, 3 Feb 2018 20:22:00 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 7606R2P5M8; Sat, 03 Feb 2018 20:22:00 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:21:56 +0800 Message-Id: <1517660516-22297-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 10/14] ARM: dts: rockchip: Enable integrated phy support for rk3229-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- arch/arm/dts/rk3229-evb.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ae0b0a4..547c7a2 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -63,7 +63,29 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; + status = "disabled"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-supply = <&vcc_phy>; + phy-mode = "rmii"; + phy-handle = <&phy>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-is-integrated; + }; + }; }; &emmc { From patchwork Sat Feb 3 12:22:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868897 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY305sxHz9t5x for ; Sat, 3 Feb 2018 23:25:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 50E7FC21E43; Sat, 3 Feb 2018 12:23:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E1305C21E40; Sat, 3 Feb 2018 12:23:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C6B6C21D9F; Sat, 3 Feb 2018 12:22:31 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.136]) by lists.denx.de (Postfix) with ESMTPS id B1393C21E16 for ; Sat, 3 Feb 2018 12:22:30 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.128]) by regular1.263xmail.com (Postfix) with ESMTP id 255883C; Sat, 3 Feb 2018 20:22:27 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id E95C43D6; Sat, 3 Feb 2018 20:22:26 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 26867M1XPO6; Sat, 03 Feb 2018 20:22:27 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:22:24 +0800 Message-Id: <1517660544-22363-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 11/14] clk: rk3328: Implement the gmac2phy clock assignment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement the setting parent and rate for gmac2phy clock, and add internal pll div set for gmac2phy clk. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk3328.c | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 3f8cdc0..c576262 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -95,6 +95,14 @@ enum { PCLK_DBG_DIV_SHIFT = 0, PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT, + /* CLKSEL_CON26 */ + GMAC2PHY_PLL_SEL_SHIFT = 7, + GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT, + GMAC2PHY_PLL_SEL_CPLL = 0, + GMAC2PHY_PLL_SEL_GPLL = 1, + GMAC2PHY_CLK_DIV_MASK = 0x1f, + GMAC2PHY_CLK_DIV_SHIFT = 0, + /* CLKSEL_CON27 */ GMAC2IO_PLL_SEL_SHIFT = 7, GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, @@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate) return ret; } +static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate) +{ + u32 con = readl(&cru->clksel_con[26]); + ulong pll_rate; + u8 div; + + if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL) + pll_rate = GPLL_HZ; + else + pll_rate = CPLL_HZ; + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, + div << GMAC2PHY_CLK_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); +} + +static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate) +{ + struct rk3328_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (readl(&grf->mac_con[2]) & BIT(10)) + /* An external clock will always generate the right rate... */ + return rate; + else + return rk3328_gmac2phy_src_set_clk(cru, rate); +} + static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) { u32 div, con, con_id; @@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_MAC2IO: ret = rk3328_gmac2io_set_clk(priv->cru, rate); break; + case SCLK_MAC2PHY: + ret = rk3328_gmac2phy_set_clk(priv->cru, rate); + break; + case SCLK_MAC2PHY_SRC: + ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate); + break; case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; @@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent) return -EINVAL; } +static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3328_grf_regs *grf; + const char *clock_output_name; + int ret; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* + * If the requested parent is in the same clock-controller and the id + * is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal clock. + */ + if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) { + debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__); + rk_clrreg(&grf->mac_con[2], BIT(10)); + return 0; + } + + /* + * Otherwise, we need to check the clock-output-names of the + * requested parent to see if the requested id is "phy_50m_out". + */ + ret = dev_read_string_index(parent->dev, "clock-output-names", + parent->id, &clock_output_name); + if (ret < 0) + return -ENODATA; + + /* If this is "phy_50m_out", switch to the external clock input */ + if (!strcmp(clock_output_name, "phy_50m_out")) { + debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__); + rk_setreg(&grf->mac_con[2], BIT(10)); + return 0; + } + + return -EINVAL; +} + static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) { switch (clk->id) { @@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) return rk3328_gmac2io_set_parent(clk, parent); case SCLK_MAC2IO_EXT: return rk3328_gmac2io_ext_set_parent(clk, parent); + case SCLK_MAC2PHY: + return rk3328_gmac2phy_set_parent(clk, parent); case DCLK_LCDC: case SCLK_PDM: case SCLK_RTC32K: From patchwork Sat Feb 3 12:22:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868896 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY2j2sNXz9t5x for ; Sat, 3 Feb 2018 23:25:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C5714C21DD9; Sat, 3 Feb 2018 12:24:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 09462C21E30; Sat, 3 Feb 2018 12:24:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BA5A7C21E55; Sat, 3 Feb 2018 12:22:59 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.131]) by lists.denx.de (Postfix) with ESMTPS id 848F8C21E1E for ; Sat, 3 Feb 2018 12:22:58 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.128]) by regular1.263xmail.com (Postfix) with ESMTP id 6B0635E08; Sat, 3 Feb 2018 20:22:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 6115D308; Sat, 3 Feb 2018 20:22:54 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 26867V3D2HV; Sat, 03 Feb 2018 20:22:54 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:22:44 +0800 Message-Id: <1517660564-22428-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 12/14] ARM: dts: rockchip: Add gmac2phy dts node for rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 5de1059..7026601 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -475,6 +475,41 @@ status = "disabled"; }; + gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-is-integrated; + }; + }; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>; From patchwork Sat Feb 3 12:23:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868899 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY4S2yBHz9t5s for ; Sat, 3 Feb 2018 23:26:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D3F64C21DE5; Sat, 3 Feb 2018 12:26:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B1580C21E26; Sat, 3 Feb 2018 12:26:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A3193C21E18; Sat, 3 Feb 2018 12:23:30 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.140]) by lists.denx.de (Postfix) with ESMTPS id 5BC73C21E3A for ; Sat, 3 Feb 2018 12:23:26 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.160]) by regular1.263xmail.com (Postfix) with ESMTP id C47514A3F; Sat, 3 Feb 2018 20:23:20 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id BA3C5393; Sat, 3 Feb 2018 20:23:20 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <626a04bad87d147110f3608f5720bf45> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 21026P9WKM3; Sat, 03 Feb 2018 20:23:21 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:23:17 +0800 Message-Id: <1517660597-22496-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 13/14] ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In fact, the rk3328-evb is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- arch/arm/dts/rk3328-evb.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 336c2d5..1e09f7d 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -101,6 +101,16 @@ pinctrl-0 = <&rgmiim1_pins>; tx_delay = <0x26>; rx_delay = <0x11>; + status = "disabled"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; status = "okay"; }; From patchwork Sat Feb 3 12:23:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868900 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYY4t6hyZz9t5s for ; Sat, 3 Feb 2018 23:26:54 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 79950C21E45; Sat, 3 Feb 2018 12:26:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2B6BCC21C51; Sat, 3 Feb 2018 12:25:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 82A0AC21E41; Sat, 3 Feb 2018 12:23:46 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.135]) by lists.denx.de (Postfix) with ESMTPS id CC481C21DD7 for ; Sat, 3 Feb 2018 12:23:42 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.8]) by regular1.263xmail.com (Postfix) with ESMTP id 19B791D8C4; Sat, 3 Feb 2018 20:23:38 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 445FE308; Sat, 3 Feb 2018 20:23:39 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith ESMTP id 28725CF9DZ1; Sat, 03 Feb 2018 20:23:39 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:23:36 +0800 Message-Id: <1517660616-22557-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 14/14] rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and rk3328-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The integtated phy inside the rk3229 and rk3328 need the reset request for power up. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 39469b4..311019d 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -40,6 +40,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3d8c04d..12497fa 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000