diff mbox

[U-Boot,v2,14/63] x86: ivybridge: Add more debugging for failures

Message ID 1479587152-25065-15-git-send-email-sjg@chromium.org
State Accepted
Commit 8d8f3acda976f2f400df660b8da12b9b2c702986
Delegated to: Bin Meng
Headers show

Commit Message

Simon Glass Nov. 19, 2016, 8:25 p.m. UTC 
Add various debug() messages in places where errors occur. This aids with
debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Output error code values in debug() statements

 arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
 arch/x86/cpu/ivybridge/sdram.c | 37 ++++++++++++++++++++++++++++---------
 2 files changed, 31 insertions(+), 10 deletions(-)

Comments

Bin Meng Dec. 19, 2016, 7:58 a.m. UTC | #1 
On Sun, Nov 20, 2016 at 4:25 AM, Simon Glass <sjg@chromium.org> wrote:
> Add various debug() messages in places where errors occur. This aids with
> debugging.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Output error code values in debug() statements
>
>  arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
>  arch/x86/cpu/ivybridge/sdram.c | 37 ++++++++++++++++++++++++++++---------
>  2 files changed, 31 insertions(+), 10 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox

Patch

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 85e361a..c4aca08 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -169,8 +169,10 @@  int print_cpuinfo(void)
 
 	/* Enable SPD ROMs and DDR-III DRAM */
 	ret = uclass_first_device_err(UCLASS_I2C, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	/* Prepare USB controller early in S3 resume */
 	if (boot_mode == PEI_BOOT_RESUME) {
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e0b06b5..201368c 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -207,8 +207,10 @@  static int copy_spd(struct udevice *dev, struct pei_data *peid)
 	int ret;
 
 	ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
 
@@ -460,18 +462,27 @@  int dram_init(void)
 
 	/* We need the pinctrl set up early */
 	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get northbridge (ret=%d)\n", __func__,
+		      ret);
 		return ret;
+	}
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	ret = copy_spd(dev, pei_data);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	pei_data->boot_mode = gd->arch.pei_boot_mode;
 	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
 	debug("mrc_input %p\n", pei_data->mrc_input);
@@ -498,19 +509,27 @@  int dram_init(void)
 
 	/* Wait for ME to be ready */
 	ret = intel_early_me_init(me_dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	ret = intel_early_me_uma_size(me_dev);
-	if (ret < 0)
+	if (ret < 0) {
+		debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = mrc_common_init(dev, pei_data, false);
-	if (ret)
+	if (ret) {
+		debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = sdram_find(dev);
-	if (ret)
+	if (ret) {
+		debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 
 	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,