| Message ID | 1439247603-8990-1-git-send-email-marex@denx.de |
|---|---|
| State | Accepted |
| Delegated to: | Marek Vasut |
| Headers | show |
On 8/10/15 6:00 PM, Marek Vasut wrote: > Based on observation, this udelay(20) was apparently too high and caused > subsequent failure to calibrate DDR when U-Boot was compiled with certain > toolchains. Lowering this delay fixed the problem. > > Instead of permanently lowering the delay, calculate the correct delay > based on the original comment, that is, obtain EOSC1 frequency and use > it to calculate the precise delay. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c > index 0be643c..2b16795 100644 > --- a/arch/arm/mach-socfpga/freeze_controller.c > +++ b/arch/arm/mach-socfpga/freeze_controller.c > @@ -7,8 +7,8 @@ > Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Thanks, Dinh
On Tuesday, August 18, 2015 at 10:27:29 PM, Dinh Nguyen wrote: > On 8/10/15 6:00 PM, Marek Vasut wrote: > > Based on observation, this udelay(20) was apparently too high and caused > > subsequent failure to calibrate DDR when U-Boot was compiled with certain > > toolchains. Lowering this delay fixed the problem. > > > > Instead of permanently lowering the delay, calculate the correct delay > > based on the original comment, that is, obtain EOSC1 frequency and use > > it to calculate the precise delay. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > --- > > > > arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- > > 1 file changed, 5 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/freeze_controller.c > > b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 > > 100644 > > --- a/arch/arm/mach-socfpga/freeze_controller.c > > +++ b/arch/arm/mach-socfpga/freeze_controller.c > > @@ -7,8 +7,8 @@ > > Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Applied to u-boot-socfpga/master, thanks! Best regards, Marek Vasut
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/clock_manager.h> #include <asm/arch/freeze_controller.h> -#include <asm/arch/timer.h> #include <asm/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +112,7 @@ void sys_mgr_frzctrl_thaw_req(void) u32 reg_cfg_mask; u32 reg_value; u32 channel_id; + unsigned long eosc1_freq; /* select software FSM */ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); @@ -162,12 +163,9 @@ void sys_mgr_frzctrl_thaw_req(void) setbits_le32(&freeze_controller_base->hioctrl, SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); + /* Delay 1000 intosc cycles. The intosc is based on eosc1. */ + eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */ + udelay(DIV_ROUND_UP(1000000, eosc1_freq)); /* * de-assert active low bhniotri signals,
Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de> --- arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-)