From patchwork Mon Aug 10 23:00:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 505818 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C8F651402BC for ; Tue, 11 Aug 2015 09:00:19 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9596A4BA9F; Tue, 11 Aug 2015 01:00:18 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LaFu7bdvJJNp; Tue, 11 Aug 2015 01:00:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 44C184B9ED; Tue, 11 Aug 2015 01:00:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50B304BA9B for ; Tue, 11 Aug 2015 01:00:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KL8YyI2Agn4k for ; Tue, 11 Aug 2015 01:00:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 0A5AF4BA90 for ; Tue, 11 Aug 2015 01:00:10 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3mqt6f25Kkz3hj8b; Tue, 11 Aug 2015 01:00:10 +0200 (CEST) X-Auth-Info: hnbox6MRgKJhEYJxtvfmAhSsuC18DG1zKXsKx6/ka2s= Received: from chi.lan (unknown [195.140.253.167]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3mqt6f0sk5zvdWt; Tue, 11 Aug 2015 01:00:10 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Tue, 11 Aug 2015 01:00:03 +0200 Message-Id: <1439247603-8990-1-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.1.4 Cc: Marek Vasut Subject: [U-Boot] [PATCH] arm: socfpga: Fix delay in freeze controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut Acked-by: Dinh Nguyen --- arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@ #include #include +#include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +112,7 @@ void sys_mgr_frzctrl_thaw_req(void) u32 reg_cfg_mask; u32 reg_value; u32 channel_id; + unsigned long eosc1_freq; /* select software FSM */ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); @@ -162,12 +163,9 @@ void sys_mgr_frzctrl_thaw_req(void) setbits_le32(&freeze_controller_base->hioctrl, SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); + /* Delay 1000 intosc cycles. The intosc is based on eosc1. */ + eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */ + udelay(DIV_ROUND_UP(1000000, eosc1_freq)); /* * de-assert active low bhniotri signals,