| Message ID | 1437013654-29387-6-git-send-email-vikas.manocha@st.com |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: > This patch is to separate the base trigger from the read/write transfer > start addresses. This patch breaks the QSPI support on SoCFPGA. > Base trigger register address (0x1c register) corresponds to the address > which should be put on AHB bus to handle indirect transfer triggered > before. > > To handle indirect transfer we need to issue addresses from (value of 0x1c) > to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). > There are no obstacles in issuing const address just equal to 0x1c. > Important thing to note is that indirect trigger address has nothing in > common with your physical or mapped NOR Flash address. > > Transfer read/write start addresses (offset 0x68/0x78)should be programmed > with the absolute flash address to be read/written. > > plat->ahbbase has been renamed to plat->flashbase for clarity. > plat->triggerbase is added in device tree for mapped spi flash address. > > Signed-off-by: Vikas Manocha <vikas.manocha@st.com> > --- > > Changes in v2: Rebased to master > > arch/arm/dts/socfpga.dtsi | 3 ++- > arch/arm/dts/stv0991.dts | 3 ++- > drivers/spi/cadence_qspi.c | 14 +++++++------- > drivers/spi/cadence_qspi.h | 5 +++-- > drivers/spi/cadence_qspi_apb.c | 11 +++++------ > 5 files changed, 19 insertions(+), 17 deletions(-) > > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi > index 9b12420..1099a92 100644 > --- a/arch/arm/dts/socfpga.dtsi > +++ b/arch/arm/dts/socfpga.dtsi > @@ -633,7 +633,8 @@ > #address-cells = <1>; > #size-cells = <0>; > reg = <0xff705000 0x1000>, > - <0xffa00000 0x1000>; > + <0xffa00000 0x1000>, > + <0x00000000 0x0010>; Shouldn't there be a phandle to > interrupts = <0 151 4>; > clocks = <&qspi_clk>; > ext-decoder = <0>; /* external decoder */ > diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts > index fa3fd64..e23d4fd 100644 > --- a/arch/arm/dts/stv0991.dts > +++ b/arch/arm/dts/stv0991.dts > @@ -30,7 +30,8 @@ > #address-cells = <1>; > #size-cells = <0>; > reg = <0x80203000 0x100>, > - <0x40000000 0x1000000>; > + <0x40000000 0x1000000>, > + <0x40000000 0x0000010>; > clocks = <3750000>; > sram-size = <256>; > status = "okay"; > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index 34a0f46..95c9cea 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) > struct cadence_spi_priv *priv = dev_get_priv(bus); > > priv->regbase = plat->regbase; > - priv->ahbbase = plat->ahbbase; > + priv->flashbase = plat->flashbase; > > if (!priv->qspi_is_init) { > cadence_qspi_apb_controller_init(plat); > @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct > udevice *bus) const void *blob = gd->fdt_blob; > int node = bus->of_offset; > int subnode; > - u32 data[4]; > + u32 data[6]; > int ret; > > /* 2 base addresses are needed, lets get them from the DT */ > @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct > udevice *bus) } > > plat->regbase = (void *)data[0]; > - plat->ahbbase = (void *)data[2]; > + plat->flashbase = (void *)data[2]; > + plat->trigger_base = (void *)data[4]; > > /* Use 500KHz as a suitable default */ > plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", > @@ -311,10 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct > udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", > 20); > plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); > > - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", > - __func__, plat->regbase, plat->ahbbase, plat->max_hz, > - plat->page_size); > - > + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ > + page-size=%d\n", __func__, plat->regbase, plat->flashbase, Please never break formating strings, they are the only exception from the 80 alignment rule. It is not possible to grep for them if they're broken. > + plat->trigger_base, plat->max_hz, plat->page_size); > return 0; > } [...]
Hi Marek, On 08/12/2015 07:15 PM, Marek Vasut wrote: > On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: >> This patch is to separate the base trigger from the read/write transfer >> start addresses. > > This patch breaks the QSPI support on SoCFPGA. ok, can you please try to debug the issue. Logically this patch looks good to me unless there is something specific to socfpga. I think latest linux v2 patch from Graham has implemented the same patch. > >> Base trigger register address (0x1c register) corresponds to the address >> which should be put on AHB bus to handle indirect transfer triggered >> before. >> >> To handle indirect transfer we need to issue addresses from (value of 0x1c) >> to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). >> There are no obstacles in issuing const address just equal to 0x1c. >> Important thing to note is that indirect trigger address has nothing in >> common with your physical or mapped NOR Flash address. >> >> Transfer read/write start addresses (offset 0x68/0x78)should be programmed >> with the absolute flash address to be read/written. >> >> plat->ahbbase has been renamed to plat->flashbase for clarity. >> plat->triggerbase is added in device tree for mapped spi flash address. >> >> Signed-off-by: Vikas Manocha <vikas.manocha@st.com> >> --- >> >> Changes in v2: Rebased to master >> >> arch/arm/dts/socfpga.dtsi | 3 ++- >> arch/arm/dts/stv0991.dts | 3 ++- >> drivers/spi/cadence_qspi.c | 14 +++++++------- >> drivers/spi/cadence_qspi.h | 5 +++-- >> drivers/spi/cadence_qspi_apb.c | 11 +++++------ >> 5 files changed, 19 insertions(+), 17 deletions(-) >> >> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi >> index 9b12420..1099a92 100644 >> --- a/arch/arm/dts/socfpga.dtsi >> +++ b/arch/arm/dts/socfpga.dtsi >> @@ -633,7 +633,8 @@ >> #address-cells = <1>; >> #size-cells = <0>; >> reg = <0xff705000 0x1000>, >> - <0xffa00000 0x1000>; >> + <0xffa00000 0x1000>, >> + <0x00000000 0x0010>; > > Shouldn't there be a phandle to > >> interrupts = <0 151 4>; >> clocks = <&qspi_clk>; >> ext-decoder = <0>; /* external decoder */ >> diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts >> index fa3fd64..e23d4fd 100644 >> --- a/arch/arm/dts/stv0991.dts >> +++ b/arch/arm/dts/stv0991.dts >> @@ -30,7 +30,8 @@ >> #address-cells = <1>; >> #size-cells = <0>; >> reg = <0x80203000 0x100>, >> - <0x40000000 0x1000000>; >> + <0x40000000 0x1000000>, >> + <0x40000000 0x0000010>; >> clocks = <3750000>; >> sram-size = <256>; >> status = "okay"; >> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c >> index 34a0f46..95c9cea 100644 >> --- a/drivers/spi/cadence_qspi.c >> +++ b/drivers/spi/cadence_qspi.c >> @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) >> struct cadence_spi_priv *priv = dev_get_priv(bus); >> >> priv->regbase = plat->regbase; >> - priv->ahbbase = plat->ahbbase; >> + priv->flashbase = plat->flashbase; >> >> if (!priv->qspi_is_init) { >> cadence_qspi_apb_controller_init(plat); >> @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct >> udevice *bus) const void *blob = gd->fdt_blob; >> int node = bus->of_offset; >> int subnode; >> - u32 data[4]; >> + u32 data[6]; >> int ret; >> >> /* 2 base addresses are needed, lets get them from the DT */ >> @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct >> udevice *bus) } >> >> plat->regbase = (void *)data[0]; >> - plat->ahbbase = (void *)data[2]; >> + plat->flashbase = (void *)data[2]; >> + plat->trigger_base = (void *)data[4]; >> >> /* Use 500KHz as a suitable default */ >> plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", >> @@ -311,10 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct >> udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", >> 20); >> plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); >> >> - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", >> - __func__, plat->regbase, plat->ahbbase, plat->max_hz, >> - plat->page_size); >> - >> + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ >> + page-size=%d\n", __func__, plat->regbase, plat->flashbase, > > Please never break formating strings, they are the only exception from the 80 > alignment rule. It is not possible to grep for them if they're broken. ok, i will fix in next version. Rgds, Vikas > >> + plat->trigger_base, plat->max_hz, plat->page_size); >> return 0; >> } > > [...] > . >
Hi Marek, On 08/13/2015 09:42 AM, vikasm wrote: > Hi Marek, > > On 08/12/2015 07:15 PM, Marek Vasut wrote: >> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: >>> This patch is to separate the base trigger from the read/write transfer >>> start addresses. >> >> This patch breaks the QSPI support on SoCFPGA. > > ok, can you please try to debug the issue. Logically this patch looks good to me unless there > is something specific to socfpga. One quick check, can you test if it works on reverting the trigger base in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000 0x1000>. Rgds, Vikas > > I think latest linux v2 patch from Graham has implemented the same patch. > >> >>> Base trigger register address (0x1c register) corresponds to the address >>> which should be put on AHB bus to handle indirect transfer triggered >>> before. >>> >>> To handle indirect transfer we need to issue addresses from (value of 0x1c) >>> to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). >>> There are no obstacles in issuing const address just equal to 0x1c. >>> Important thing to note is that indirect trigger address has nothing in >>> common with your physical or mapped NOR Flash address. >>> >>> Transfer read/write start addresses (offset 0x68/0x78)should be programmed >>> with the absolute flash address to be read/written. >>> >>> plat->ahbbase has been renamed to plat->flashbase for clarity. >>> plat->triggerbase is added in device tree for mapped spi flash address. >>> >>> Signed-off-by: Vikas Manocha <vikas.manocha@st.com> >>> --- >>> >>> Changes in v2: Rebased to master >>> >>> arch/arm/dts/socfpga.dtsi | 3 ++- >>> arch/arm/dts/stv0991.dts | 3 ++- >>> drivers/spi/cadence_qspi.c | 14 +++++++------- >>> drivers/spi/cadence_qspi.h | 5 +++-- >>> drivers/spi/cadence_qspi_apb.c | 11 +++++------ >>> 5 files changed, 19 insertions(+), 17 deletions(-) >>> >>> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi >>> index 9b12420..1099a92 100644 >>> --- a/arch/arm/dts/socfpga.dtsi >>> +++ b/arch/arm/dts/socfpga.dtsi >>> @@ -633,7 +633,8 @@ >>> #address-cells = <1>; >>> #size-cells = <0>; >>> reg = <0xff705000 0x1000>, >>> - <0xffa00000 0x1000>; >>> + <0xffa00000 0x1000>, >>> + <0x00000000 0x0010>; >> >> Shouldn't there be a phandle to >> >>> interrupts = <0 151 4>; >>> clocks = <&qspi_clk>; >>> ext-decoder = <0>; /* external decoder */ >>> diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts >>> index fa3fd64..e23d4fd 100644 >>> --- a/arch/arm/dts/stv0991.dts >>> +++ b/arch/arm/dts/stv0991.dts >>> @@ -30,7 +30,8 @@ >>> #address-cells = <1>; >>> #size-cells = <0>; >>> reg = <0x80203000 0x100>, >>> - <0x40000000 0x1000000>; >>> + <0x40000000 0x1000000>, >>> + <0x40000000 0x0000010>; >>> clocks = <3750000>; >>> sram-size = <256>; >>> status = "okay"; >>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c >>> index 34a0f46..95c9cea 100644 >>> --- a/drivers/spi/cadence_qspi.c >>> +++ b/drivers/spi/cadence_qspi.c >>> @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) >>> struct cadence_spi_priv *priv = dev_get_priv(bus); >>> >>> priv->regbase = plat->regbase; >>> - priv->ahbbase = plat->ahbbase; >>> + priv->flashbase = plat->flashbase; >>> >>> if (!priv->qspi_is_init) { >>> cadence_qspi_apb_controller_init(plat); >>> @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct >>> udevice *bus) const void *blob = gd->fdt_blob; >>> int node = bus->of_offset; >>> int subnode; >>> - u32 data[4]; >>> + u32 data[6]; >>> int ret; >>> >>> /* 2 base addresses are needed, lets get them from the DT */ >>> @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct >>> udevice *bus) } >>> >>> plat->regbase = (void *)data[0]; >>> - plat->ahbbase = (void *)data[2]; >>> + plat->flashbase = (void *)data[2]; >>> + plat->trigger_base = (void *)data[4]; >>> >>> /* Use 500KHz as a suitable default */ >>> plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", >>> @@ -311,10 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct >>> udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", >>> 20); >>> plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); >>> >>> - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", >>> - __func__, plat->regbase, plat->ahbbase, plat->max_hz, >>> - plat->page_size); >>> - >>> + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ >>> + page-size=%d\n", __func__, plat->regbase, plat->flashbase, >> >> Please never break formating strings, they are the only exception from the 80 >> alignment rule. It is not possible to grep for them if they're broken. > > ok, i will fix in next version. > > Rgds, > Vikas > >> >>> + plat->trigger_base, plat->max_hz, plat->page_size); >>> return 0; >>> } >> >> [...] >> . >>
On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: > Hi Marek, Hi! > On 08/13/2015 09:42 AM, vikasm wrote: > > Hi Marek, > > > > On 08/12/2015 07:15 PM, Marek Vasut wrote: > >> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: > >>> This patch is to separate the base trigger from the read/write transfer > >>> start addresses. > >> > >> This patch breaks the QSPI support on SoCFPGA. > > > > ok, can you please try to debug the issue. Logically this patch looks > > good to me unless there is something specific to socfpga. > > One quick check, can you test if it works on reverting the trigger base in > arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000 0x1000>. Can you please spin V3 of the patchset first, one which omits the buggy bits, so I can test it on a more final form of the patches ? Please keep me on CC, I'll test it then. Thanks! Best regards, Marek Vasut
Hi, On 08/13/2015 03:48 PM, Marek Vasut wrote: > On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: >> Hi Marek, > > Hi! > >> On 08/13/2015 09:42 AM, vikasm wrote: >>> Hi Marek, >>> >>> On 08/12/2015 07:15 PM, Marek Vasut wrote: >>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: >>>>> This patch is to separate the base trigger from the read/write transfer >>>>> start addresses. >>>> >>>> This patch breaks the QSPI support on SoCFPGA. >>> >>> ok, can you please try to debug the issue. Logically this patch looks >>> good to me unless there is something specific to socfpga. >> >> One quick check, can you test if it works on reverting the trigger base in >> arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000 0x1000>. > > Can you please spin V3 of the patchset first, one which omits the buggy bits, > so I can test it on a more final form of the patches ? Please keep me on CC, > I'll test it then. Once i add sram level test patches, i would not be able to test it on my platform. This particular issue is pending for long time. I suggest to debug (at least with above mentioned quick test) this particular issue/patch with current version v2. There is only minor change (format string) in this patch for v3. Rgds, Vikas > > Thanks! > > Best regards, > Marek Vasut > . >
On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: > Hi, > > On 08/13/2015 03:48 PM, Marek Vasut wrote: > > On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: > >> Hi Marek, > > > > Hi! > > > >> On 08/13/2015 09:42 AM, vikasm wrote: > >>> Hi Marek, > >>> > >>> On 08/12/2015 07:15 PM, Marek Vasut wrote: > >>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: > >>>>> This patch is to separate the base trigger from the read/write > >>>>> transfer start addresses. > >>>> > >>>> This patch breaks the QSPI support on SoCFPGA. > >>> > >>> ok, can you please try to debug the issue. Logically this patch looks > >>> good to me unless there is something specific to socfpga. > >> > >> One quick check, can you test if it works on reverting the trigger base > >> in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000 > >> 0x1000>. > > > > Can you please spin V3 of the patchset first, one which omits the buggy > > bits, so I can test it on a more final form of the patches ? Please keep > > me on CC, I'll test it then. > > Once i add sram level test patches, i would not be able to test it on my > platform. This particular issue is pending for long time. I suggest to > debug (at least with above mentioned quick test) this particular > issue/patch with current version v2. There is only minor change (format > string) in this patch for v3. That's fine, just send the V3 as RFT and I'll check it. Best regards, Marek Vasut
Hi Marek, On 08/13/2015 06:04 PM, Marek Vasut wrote: > On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: >> Hi, >> >> On 08/13/2015 03:48 PM, Marek Vasut wrote: >>> On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: >>>> Hi Marek, >>> >>> Hi! >>> >>>> On 08/13/2015 09:42 AM, vikasm wrote: >>>>> Hi Marek, >>>>> >>>>> On 08/12/2015 07:15 PM, Marek Vasut wrote: >>>>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: >>>>>>> This patch is to separate the base trigger from the read/write >>>>>>> transfer start addresses. >>>>>> >>>>>> This patch breaks the QSPI support on SoCFPGA. >>>>> >>>>> ok, can you please try to debug the issue. Logically this patch looks >>>>> good to me unless there is something specific to socfpga. >>>> >>>> One quick check, can you test if it works on reverting the trigger base >>>> in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to <0xffa00000 >>>> 0x1000>. >>> >>> Can you please spin V3 of the patchset first, one which omits the buggy >>> bits, so I can test it on a more final form of the patches ? Please keep >>> me on CC, I'll test it then. >> >> Once i add sram level test patches, i would not be able to test it on my >> platform. This particular issue is pending for long time. I suggest to >> debug (at least with above mentioned quick test) this particular >> issue/patch with current version v2. There is only minor change (format >> string) in this patch for v3. > > That's fine, just send the V3 as RFT and I'll check it. If this patch is not debugged, there is no major significance of this patchset. I would appreciate if you do some test with current v2. Rgds, Vikas > > Best regards, > Marek Vasut > . >
On Friday, August 14, 2015 at 03:39:22 AM, vikas wrote: > Hi Marek, > > On 08/13/2015 06:04 PM, Marek Vasut wrote: > > On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: > >> Hi, > >> > >> On 08/13/2015 03:48 PM, Marek Vasut wrote: > >>> On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: > >>>> Hi Marek, > >>> > >>> Hi! > >>> > >>>> On 08/13/2015 09:42 AM, vikasm wrote: > >>>>> Hi Marek, > >>>>> > >>>>> On 08/12/2015 07:15 PM, Marek Vasut wrote: > >>>>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: > >>>>>>> This patch is to separate the base trigger from the read/write > >>>>>>> transfer start addresses. > >>>>>> > >>>>>> This patch breaks the QSPI support on SoCFPGA. > >>>>> > >>>>> ok, can you please try to debug the issue. Logically this patch looks > >>>>> good to me unless there is something specific to socfpga. > >>>> > >>>> One quick check, can you test if it works on reverting the trigger > >>>> base in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to > >>>> <0xffa00000 0x1000>. > >>> > >>> Can you please spin V3 of the patchset first, one which omits the buggy > >>> bits, so I can test it on a more final form of the patches ? Please > >>> keep me on CC, I'll test it then. > >> > >> Once i add sram level test patches, i would not be able to test it on my > >> platform. This particular issue is pending for long time. I suggest to > >> debug (at least with above mentioned quick test) this particular > >> issue/patch with current version v2. There is only minor change (format > >> string) in this patch for v3. > > > > That's fine, just send the V3 as RFT and I'll check it. > > If this patch is not debugged, there is no major significance of this > patchset. I would appreciate if you do some test with current v2. I stop here for today and will get back to this in a few days again. Please send V3 until then, I don't want to dig in old/broken code. Best regards, Marek Vasut
Hi, > On Aug 13, 2015, at 6:57 PM, Marek Vasut <marex@denx.de> wrote: > >> On Friday, August 14, 2015 at 03:39:22 AM, vikas wrote: >> Hi Marek, >> >>> On 08/13/2015 06:04 PM, Marek Vasut wrote: >>>> On Friday, August 14, 2015 at 02:37:53 AM, vikas wrote: >>>> Hi, >>>> >>>>> On 08/13/2015 03:48 PM, Marek Vasut wrote: >>>>>> On Thursday, August 13, 2015 at 11:36:31 PM, vikas wrote: >>>>>> Hi Marek, >>>>> >>>>> Hi! >>>>> >>>>>>> On 08/13/2015 09:42 AM, vikasm wrote: >>>>>>> Hi Marek, >>>>>>> >>>>>>>> On 08/12/2015 07:15 PM, Marek Vasut wrote: >>>>>>>>> On Thursday, July 16, 2015 at 04:27:33 AM, Vikas Manocha wrote: >>>>>>>>> This patch is to separate the base trigger from the read/write >>>>>>>>> transfer start addresses. >>>>>>>> >>>>>>>> This patch breaks the QSPI support on SoCFPGA. >>>>>>> >>>>>>> ok, can you please try to debug the issue. Logically this patch looks >>>>>>> good to me unless there is something specific to socfpga. >>>>>> >>>>>> One quick check, can you test if it works on reverting the trigger >>>>>> base in arch/arm/dts/socfpga.dtsi from <0x00000000 0x0010> to >>>>>> <0xffa00000 0x1000>. >>>>> >>>>> Can you please spin V3 of the patchset first, one which omits the buggy >>>>> bits, so I can test it on a more final form of the patches ? Please >>>>> keep me on CC, I'll test it then. >>>> >>>> Once i add sram level test patches, i would not be able to test it on my >>>> platform. This particular issue is pending for long time. I suggest to >>>> debug (at least with above mentioned quick test) this particular >>>> issue/patch with current version v2. There is only minor change (format >>>> string) in this patch for v3. >>> >>> That's fine, just send the V3 as RFT and I'll check it. >> >> If this patch is not debugged, there is no major significance of this >> patchset. I would appreciate if you do some test with current v2. > > I stop here for today and will get back to this in a few days again. > Please send V3 until then, I don't want to dig in old/broken code. Ok, I will send the v3 tomorrow. Rgds, Vikas > > Best regards, > Marek Vasut
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 9b12420..1099a92 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -633,7 +633,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; + <0xffa00000 0x1000>, + <0x00000000 0x0010>; interrupts = <0 151 4>; clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index fa3fd64..e23d4fd 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -30,7 +30,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80203000 0x100>, - <0x40000000 0x1000000>; + <0x40000000 0x1000000>, + <0x40000000 0x0000010>; clocks = <3750000>; sram-size = <256>; status = "okay"; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..95c9cea 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) struct cadence_spi_priv *priv = dev_get_priv(bus); priv->regbase = plat->regbase; - priv->ahbbase = plat->ahbbase; + priv->flashbase = plat->flashbase; if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = bus->of_offset; int subnode; - u32 data[4]; + u32 data[6]; int ret; /* 2 base addresses are needed, lets get them from the DT */ @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) } plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; + plat->flashbase = (void *)data[2]; + plat->trigger_base = (void *)data[4]; /* Use 500KHz as a suitable default */ plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", @@ -311,10 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", - __func__, plat->regbase, plat->ahbbase, plat->max_hz, - plat->page_size); - + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ + page-size=%d\n", __func__, plat->regbase, plat->flashbase, + plat->trigger_base, plat->max_hz, plat->page_size); return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..7341339 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -17,7 +17,8 @@ struct cadence_spi_platdata { unsigned int max_hz; void *regbase; - void *ahbbase; + void *flashbase; + void *trigger_base; u32 page_size; u32 block_size; @@ -30,7 +31,7 @@ struct cadence_spi_platdata { struct cadence_spi_priv { void *regbase; - void *ahbbase; + void *flashbase; size_t cmd_len; u8 cmd_buf[32]; size_t data_len; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7313b0c..e11f715 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -44,7 +44,6 @@ #define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -219,7 +218,7 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, const void *src_addr, unsigned int num_bytes) { int i = 0; - unsigned int *dest_addr = plat->ahbbase; + unsigned int *dest_addr = plat->trigger_base; unsigned int wr_bytes; unsigned int *src_ptr = (unsigned int *)src_addr; int remaining = num_bytes; @@ -467,7 +466,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) /* Indirect mode configurations */ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->trigger_base, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Disable all interrupts */ @@ -638,7 +637,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + addr_value, + writel((u32)plat->flashbase + addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); /* The remaining lenght is dummy bytes. */ @@ -687,7 +686,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, udelay(1); if (cadence_qspi_apb_read_fifo_data((void *)rxbuf, - (const void *)plat->ahbbase, rxlen)) + (const void *)plat->trigger_base, rxlen)) goto failrd; /* Check flash indirect controller */ @@ -730,7 +729,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, /* Setup write address. */ reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + reg, + writel((u32)plat->flashbase + reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); reg = readl(plat->regbase + CQSPI_REG_SIZE);
This patch is to separate the base trigger from the read/write transfer start addresses. Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer triggered before. To handle indirect transfer we need to issue addresses from (value of 0x1c) to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). There are no obstacles in issuing const address just equal to 0x1c. Important thing to note is that indirect trigger address has nothing in common with your physical or mapped NOR Flash address. Transfer read/write start addresses (offset 0x68/0x78)should be programmed with the absolute flash address to be read/written. plat->ahbbase has been renamed to plat->flashbase for clarity. plat->triggerbase is added in device tree for mapped spi flash address. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> --- Changes in v2: Rebased to master arch/arm/dts/socfpga.dtsi | 3 ++- arch/arm/dts/stv0991.dts | 3 ++- drivers/spi/cadence_qspi.c | 14 +++++++------- drivers/spi/cadence_qspi.h | 5 +++-- drivers/spi/cadence_qspi_apb.c | 11 +++++------ 5 files changed, 19 insertions(+), 17 deletions(-)