From patchwork Thu Jul 16 02:27:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 496530 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EA1311402B2 for ; Thu, 16 Jul 2015 12:35:56 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F2C94B6B1; Thu, 16 Jul 2015 04:35:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ci_YjbQxHB9k; Thu, 16 Jul 2015 04:35:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0E1764B6B2; Thu, 16 Jul 2015 04:35:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B58D14B64D for ; Thu, 16 Jul 2015 04:35:21 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TfnQsDAaMBmy for ; Thu, 16 Jul 2015 04:35:21 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by theia.denx.de (Postfix) with ESMTPS id 51F3D4B65F for ; Thu, 16 Jul 2015 04:35:11 +0200 (CEST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id t6G2WuCA018823; Thu, 16 Jul 2015 04:35:10 +0200 Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx08-00178001.pphosted.com with ESMTP id 1vnt5wt65c-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 16 Jul 2015 04:35:10 +0200 Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 14EC724; Thu, 16 Jul 2015 02:35:06 +0000 (GMT) Received: from Webmail-ap.st.com (eapex1hubcas2.st.com [10.80.176.10]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A991B92B; Thu, 16 Jul 2015 02:35:04 +0000 (GMT) Received: from localhost (10.41.34.229) by Webmail-ap.st.com (10.80.176.7) with Microsoft SMTP Server (TLS) id 8.3.342.0; Thu, 16 Jul 2015 10:35:02 +0800 From: Vikas Manocha To: , , , Date: Wed, 15 Jul 2015 19:27:33 -0700 Message-ID: <1437013654-29387-6-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437013654-29387-1-git-send-email-vikas.manocha@st.com> References: <1437013654-29387-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.14.151, 1.0.33, 0.0.0000 definitions=2015-07-15_07:2015-07-15, 2015-07-15, 1970-01-01 signatures=0 Subject: [U-Boot] [v2 5/6] spi: cadence_qspi: fix base trigger address & transfer start address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch is to separate the base trigger from the read/write transfer start addresses. Base trigger register address (0x1c register) corresponds to the address which should be put on AHB bus to handle indirect transfer triggered before. To handle indirect transfer we need to issue addresses from (value of 0x1c) to (value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location). There are no obstacles in issuing const address just equal to 0x1c. Important thing to note is that indirect trigger address has nothing in common with your physical or mapped NOR Flash address. Transfer read/write start addresses (offset 0x68/0x78)should be programmed with the absolute flash address to be read/written. plat->ahbbase has been renamed to plat->flashbase for clarity. plat->triggerbase is added in device tree for mapped spi flash address. Signed-off-by: Vikas Manocha --- Changes in v2: Rebased to master arch/arm/dts/socfpga.dtsi | 3 ++- arch/arm/dts/stv0991.dts | 3 ++- drivers/spi/cadence_qspi.c | 14 +++++++------- drivers/spi/cadence_qspi.h | 5 +++-- drivers/spi/cadence_qspi_apb.c | 11 +++++------ 5 files changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 9b12420..1099a92 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -633,7 +633,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, - <0xffa00000 0x1000>; + <0xffa00000 0x1000>, + <0x00000000 0x0010>; interrupts = <0 151 4>; clocks = <&qspi_clk>; ext-decoder = <0>; /* external decoder */ diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index fa3fd64..e23d4fd 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -30,7 +30,8 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x80203000 0x100>, - <0x40000000 0x1000000>; + <0x40000000 0x1000000>, + <0x40000000 0x0000010>; clocks = <3750000>; sram-size = <256>; status = "okay"; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..95c9cea 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus) struct cadence_spi_priv *priv = dev_get_priv(bus); priv->regbase = plat->regbase; - priv->ahbbase = plat->ahbbase; + priv->flashbase = plat->flashbase; if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(plat); @@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = bus->of_offset; int subnode; - u32 data[4]; + u32 data[6]; int ret; /* 2 base addresses are needed, lets get them from the DT */ @@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) } plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; + plat->flashbase = (void *)data[2]; + plat->trigger_base = (void *)data[4]; /* Use 500KHz as a suitable default */ plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", @@ -311,10 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", - __func__, plat->regbase, plat->ahbbase, plat->max_hz, - plat->page_size); - + debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ + page-size=%d\n", __func__, plat->regbase, plat->flashbase, + plat->trigger_base, plat->max_hz, plat->page_size); return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..7341339 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -17,7 +17,8 @@ struct cadence_spi_platdata { unsigned int max_hz; void *regbase; - void *ahbbase; + void *flashbase; + void *trigger_base; u32 page_size; u32 block_size; @@ -30,7 +31,7 @@ struct cadence_spi_platdata { struct cadence_spi_priv { void *regbase; - void *ahbbase; + void *flashbase; size_t cmd_len; u8 cmd_buf[32]; size_t data_len; diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7313b0c..e11f715 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -44,7 +44,6 @@ #define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -219,7 +218,7 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, const void *src_addr, unsigned int num_bytes) { int i = 0; - unsigned int *dest_addr = plat->ahbbase; + unsigned int *dest_addr = plat->trigger_base; unsigned int wr_bytes; unsigned int *src_ptr = (unsigned int *)src_addr; int remaining = num_bytes; @@ -467,7 +466,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) /* Indirect mode configurations */ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->trigger_base, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Disable all interrupts */ @@ -638,7 +637,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + addr_value, + writel((u32)plat->flashbase + addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); /* The remaining lenght is dummy bytes. */ @@ -687,7 +686,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, udelay(1); if (cadence_qspi_apb_read_fifo_data((void *)rxbuf, - (const void *)plat->ahbbase, rxlen)) + (const void *)plat->trigger_base, rxlen)) goto failrd; /* Check flash indirect controller */ @@ -730,7 +729,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, /* Setup write address. */ reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); - writel((u32)plat->ahbbase + reg, + writel((u32)plat->flashbase + reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); reg = readl(plat->regbase + CQSPI_REG_SIZE);