diff mbox

[U-Boot,2/5] arm1176/cpu: Add icache and dcache support

Message ID 1436003324-8769-3-git-send-email-alexanders83@web.de
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Alexander Stein July 4, 2015, 9:48 a.m. UTC 
The code is copied 1:1 from arm1136 which uses the same cp15 registers.

Signed-off-by: Alexander Stein <alexanders83@web.de>
---
 arch/arm/cpu/arm1176/cpu.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 97 insertions(+)

Comments

Stephen Warren July 11, 2015, 5:21 a.m. UTC | #1 
On 07/04/2015 03:48 AM, Alexander Stein wrote:
> The code is copied 1:1 from arm1136 which uses the same cp15 registers.

Same comment here. Perhaps create a cache-armv6.c (or whatever name is
appropriate; I'm not sure if ARMv6 mandates caches work this way, or if
ARM11 is a better name, or ...?
Alexander Stein July 12, 2015, 7:26 a.m. UTC | #2 
On Friday 10 July 2015, 23:21:32 wrote Stephen Warren:
> On 07/04/2015 03:48 AM, Alexander Stein wrote:
> > The code is copied 1:1 from arm1136 which uses the same cp15 registers.
> 
> Same comment here. Perhaps create a cache-armv6.c (or whatever name is
> appropriate; I'm not sure if ARMv6 mandates caches work this way, or if
> ARM11 is a better name, or ...?

I know that cortex-m0 and cortex-m1 are also ARMv6(-M). I have no idea how cache works there or even if there is any.
I think ARM11 seems more suitable for me. But where to put? Currently each CPU core has it's own directory.

Alexander
Stephen Warren July 14, 2015, 4:57 a.m. UTC | #3 
On 07/12/2015 01:26 AM, Alexander Stein wrote:
> On Friday 10 July 2015, 23:21:32 wrote Stephen Warren:
>> On 07/04/2015 03:48 AM, Alexander Stein wrote:
>>> The code is copied 1:1 from arm1136 which uses the same cp15 registers.
>>
>> Same comment here. Perhaps create a cache-armv6.c (or whatever name is
>> appropriate; I'm not sure if ARMv6 mandates caches work this way, or if
>> ARM11 is a better name, or ...?
> 
> I know that cortex-m0 and cortex-m1 are also ARMv6(-M). I have no idea how cache works there or even if there is any.
> I think ARM11 seems more suitable for me. But where to put? Currently each CPU core has it's own directory.

Perhaps create an arch/arm/cpu/arm11 or arch/arm/cpu/armv6 directory?
diff mbox

Patch

diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
index 24b5cc7..2ff0e25 100644
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -51,3 +51,100 @@  static void cache_flush(void)
 	/* mem barrier to sync things */
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
+
+void invalidate_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	if (!check_cache_range(start, stop))
+		return;
+
+	while (start < stop) {
+		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+		start += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+#endif