From patchwork Sat Jul 4 09:48:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 491216 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 03498140295 for ; Sat, 4 Jul 2015 19:54:49 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 830344B639; Sat, 4 Jul 2015 11:54:31 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0_UfjoO_DECe; Sat, 4 Jul 2015 11:54:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CCE84A03A; Sat, 4 Jul 2015 11:54:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9376D4B66A for ; Sat, 4 Jul 2015 11:54:18 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kmgOECt4-RQN for ; Sat, 4 Jul 2015 11:54:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.web.de (mout.web.de [212.227.15.14]) by theia.denx.de (Postfix) with ESMTPS id 0DDBA4B64D for ; Sat, 4 Jul 2015 11:54:10 +0200 (CEST) Received: from kongar.lan.local ([185.44.151.3]) by smtp.web.de (mrweb002) with ESMTPSA (Nemesis) id 0MCqSB-1ZJGYs41wp-009kYl; Sat, 04 Jul 2015 11:48:58 +0200 From: Alexander Stein To: Albert Aribaud , Stephen Warren Date: Sat, 4 Jul 2015 11:48:41 +0200 Message-Id: <1436003324-8769-3-git-send-email-alexanders83@web.de> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de> References: <1436003324-8769-1-git-send-email-alexanders83@web.de> X-Provags-ID: V03:K0:oCLs9iU5HDhKvP9tCMBhCwfTFF9H7T3b02k6mm53yDJ0ihUaHX9 f1zXENPEBcRsDtSozNN9WgXg/vdmLwICDOVDb/j4dyvfssDZswTExQHwkIv2q2OxLqYdiCd cZgOcEcd680yO9wOro3EzqJbqLqu1zM6ODUmcmoZuHIs8zxGJyyV5OvlWdpNd1p3xbbeh8j Iz9+WIDmeoSnFTe4pCkaQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:cjjcQujvEIM=:Vf5DMCmdRgrgGXEdQfOrLy x7YGBM+yfAZnp7NNJMo7BWS1Kajh4A0+gXeGUdhfJxKLXuebylR6ACLoBs5DENYxag25BxQmn CXZ/pICZP7vYnCX43vXZLFOCMZRU5jp73wa8PMOiVH7Yl4MggfvpO2EriBgvc6yLpz/uPpVlO 7fGCU+y4eIXDux+tM3iDlkUUi1dVNcgByOaN2p9PMOKSSU1nL66kuFM3OMm42V232HBHsr7C0 y5vRwfZTb9JcTks5BxRIKzEq/rsyXdJkteIaQLl9H2vXry69fBsLKMR1PEvJC73SL8jzbE0w6 e1AXvNvuSAebNAFzVCz6lMiufDUy1UiqssKiqpvh96nhVfBrrc4ZxRcOeNubzSolXdA+/Unng MxEfcEjpDI3juBaA+96KqLUREnqyqd5rr1K5byjsHDdy0G7fQH/jzdvjjQqQvKh0LeVGZRTR9 yqBYhu4wJURbey/IHmRm2m7dJC1pD4bqXet4PsHxfqKA6sZqkBNWdLxfouczNtRcxQX3lS5q6 6CcFmp6gCaD8haUxGL+oOoyGZyfvV/C23PrIEsySiGtYll3b0pBoJ+0x8Uk8ER2WtFHdu6aMy mVqZvskgaThCh7yk7LbC7+Oa5diNi7lkYG+RjfmzYMaoDrvgXGQKZmKqTi9eHtaBPVEACG+N+ pMx/UrSt2D2G/awzSoMgsSBQbhVQyu/mNAf+4zLaa1iehjziCvoBdHv/F0ZEO6smeJpE= Cc: Alexander Stein , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/5] arm1176/cpu: Add icache and dcache support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The code is copied 1:1 from arm1136 which uses the same cp15 registers. Signed-off-by: Alexander Stein --- arch/arm/cpu/arm1176/cpu.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index 24b5cc7..2ff0e25 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -51,3 +51,100 @@ static void cache_flush(void) /* mem barrier to sync things */ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); } + +#ifndef CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + +void invalidate_dcache_all(void) +{ + asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); +} + +void flush_dcache_all(void) +{ + asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +} + +static int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) + debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + + return ok; +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + if (!check_cache_range(start, stop)) + return; + + while (start < stop) { + asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); + start += CONFIG_SYS_CACHELINE_SIZE; + } + + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +void invalidate_dcache_all(void) +{ +} + +void flush_dcache_all(void) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_cache(unsigned long start, unsigned long size) +{ +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} +#endif